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SY10E193JZ PDF预览

SY10E193JZ

更新时间: 2024-01-22 13:44:35
品牌 Logo 应用领域
麦瑞 - MICREL 运算电路逻辑集成电路
页数 文件大小 规格书
5页 65K
描述
ERROR DETECTION/CORRECTION CIRCUIT

SY10E193JZ 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCJ,针数:28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.36Is Samacsys:N
系列:10EJESD-30 代码:S-PQCC-J28
JESD-609代码:e3长度:11.48 mm
逻辑集成电路类型:ERROR DETECTION AND CORRECTION CIRCUIT位数:8
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER传播延迟(tpd):1.15 ns
认证状态:Not Qualified座面最大高度:4.57 mm
表面贴装:YES技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD宽度:11.48 mm
Base Number Matches:1

SY10E193JZ 数据手册

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ERROR DETECTION/  
SY10E193  
SY100E193  
CORRECTION CIRCUIT  
FEATURES  
DESCRIPTION  
Hamming code generation  
Extended 100E VEE range of –4.2V to –5.5V  
8-bit wide  
The SY10/100E193 are error detection and correction  
(EDAC) circuits designed for use in new, high- performance  
ECL systems. The E193 generates hamming parity codes  
on an 8-bit word as shown in the block diagram. The P5  
output gives the parity of the whole word. PGEN provides  
word parity after Odd/Even parity control and gating with  
the BPAR input. PGEN also feeds into a 1-bit shiftable  
register for use as part of a scan ring.  
The combinatorial part of the device generates the same  
code pattern as the Motorola MC10193.  
Used in conjunction with 12-bit parity generators, such  
as the E160, a SECDED (single error correction, double  
error detection) error system can be designed for a multiple  
of an 8-bit word.  
Expandable for more width  
Provides parity register  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E193  
Available in 28-pin PLCC package  
PIN NAMES  
Pin  
Function  
Check Bit Inputs  
B0–B7  
BPAR  
EV/OD  
EN  
Check Bit Parity Input  
Even/Odd Parity Select  
Parity Enable  
HOLD  
S-IN  
Syndrome Hold Input  
Syndrome Bit Input  
Syndrome Bit Shift  
Clock Input  
SHIFT  
CLK  
P1–P5  
PGEN  
Parity Output  
Parity Generate Output  
Parity Error Output  
VCC to Output  
PARERR/PARERR  
VCCO  
Rev.: F  
Amendment: /0  
M9999-032006  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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