Datasheet > SY10E160_06

SY10E160_06

更新时间： 2024-11-29 05:04:27

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
5页	63K
描述
12-BIT PARITY GENERATOR/CHECKER

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数据手册

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SY10E160_06 数据手册

SY10E160

Micrel, Inc.

SY100E160

12-BIT PARITY

SY10E160

SY100E160

GENERATOR/CHECKER

FEATURES

DESCRIPTION

■ Provides odd-HIGH parity of 12 inputs

■ Extended 100E VEE range of –4.2V to –5.5V

■ Output register with Shift/Hold capability

■ 900ps max. D to Q, /Q output

■ Enable control

The SY10/100E160 are high-speed, 12-bit parity

generator/checkers with differential outputs, for use in

new, high-performance ECL systems. The output Q takes

on a logic HIGH value only when an odd number of inputs

are at a logic HIGH. A logic HIGH on the enable input (EN)

forces the output Q to a logic LOW.

An additional feature of the E160 is the output register.

Two multiplexers and their associated signals control the

data, loading the new parity data or shifting external data

in. To hold the present data, the Hold signal (HOLD) must

be at a logic LOW level. If the HOLD signal is at a logic

HIGH, the data present at the Q output is passed through

the first multiplexer. Taking the Shift signal (SHIFT) to a

logic HIGH will shift the data at the S-IN pin into the output

of the first multiplexer is then passed through to the register.

The register itself is clocked on the rising edge of CLK1

or CLK2 (or both). The presence of a logic HIGH on the

reset pin (R) forces the register output Y to a logic LOW.

■ Asynchronous Register Reset

■ Differential outputs

■ Fully compatible with industry standard 10KH,

100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E160

■ Available in 28-pin PLCC package

BLOCK DIAGRAM

D10

D11

MUX

SEL

MUX

SEL

HOLD

S-IN

SHIFT

CLK1

CLK2

Rev.: F

Amendment: /0

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4 5

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