Datasheet > SVF312R3K1CKU2R

SVF312R3K1CKU2R

更新时间： 2024-11-14 02:43:55

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
125页	1963K
描述
Standard JTAG

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数据手册

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SVF312R3K1CKU2R 数据手册

Document Number VYBRIDRSERIESEC

Rev. 8, 01/2018

NXP Semiconductors

Data Sheet: Technical Data

VYBRIDRSERIESEC

VF3xxR, VF5xxR

Features

• Debug

– Standard JTAG

– 16-bit Trace port

• Operating characteristics

– Voltage range 3 V to 3.6 V

– Temperature range(ambient) -40 °C to 85 °C

• Timers

– Motor control/general purpose timer (FTM)

– Periodic Interrupt Timers (PITs)

– Low-power timer (LPTMR0)

– IEEE 1588 Timer per MAC interface (part of

Ethernet Subsystem)

• ARM® Cortex® A5 Core features

– Up to 400 MHz ARM® Cortex® A5 core

– 32 KB/32 KB I/D L1 Cache

– 1.6 DMIPS/MHz based on ARMv7 architecture

– NEON™ MPE (Media Processing Engine) Co-

processor

• Communications

– Double Precision Floating Point Unit

– 512 KB L2 cache (on selected part numbers only)

– Six Universal asynchronous receivers/transmitters

(UART)/Serial communications interface (SCI) with

LIN, ISO7816, IrDA, and hardware flow control

– Four Deserial Serial peripheral interface (DSPI)

– Four Inter-Integrated Circuit (I2C) with SMBUS

support

– Dual USB OTG Controller + PHY

– Dual 4/8 bit Secure Digital Host controller

– Local Media Bus (MLB50)

• ARM Cortex M4 Core features

– Up to 133 MHz ARM Cortex M4

– Integrated DSP capability

– 64 KB Tightly Coupled Memory (TCM)

– 16 KB/16 KB I/D L1 Cache

– 1.25 DMIPS/MHz based on ARMv7 architecture

• Clocks

– Dual 10/100 Ethernet (IEEE 1588)

– Dual FlexCAN3

– 24 MHz crystal oscillator

– 32 kHz crystal oscillator

– Internal reference clocks (128 KHz and 24 MHz)

– Phase Locked Loops (PLLs)

– Low Jitter Digital PLLs

• Security

– ARM TrustZone including the TZ architecture

– Secure Non-Volatile Storage (SNVS)

– Real Time Clock

• System debug, protection, and power management

– Various stop, wait, and run modes to provide low

power based on application needs

– Real Time Integrity Checker (RTIC)

– TrustZone Watchdog (TZ WDOG)

– Trust Zone Address Space Controller

– Random Number Generator

– Hashing

– Peripheral clock enable register can disable clocks to

unused modules, thereby reducing currents

– Low voltage warning and detect with selectable trip

points

– Illegal opcode and illegal address detection with

programmable reset or processor exception response

– Hardware CRC module to support fast cyclic

redundancy checks (CRC)

– 128-bit unique chip identifier

– Hardware watchdog

– External Watchdog Monitor (EWM)

– Dual DMA controller with 32 channels (with

DMAMUX)

– Secure JTAG

• Memory Interfaces

– 8/16-bit DRAM Controller with support for

LPDDR2/DDR3 - Up to 400 MHz (ECC supported

for 8-bit only and not 16-bit)

– 8/16-bit NAND Flash controller with ECC (ECC

supported for 8-bit only and not 16-bit)

– Dual Quad SPI with XIP (Execute-In-Place)

– 8/16/32-bit External bus (Flexbus)

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

12 3 4 5 6 7...125

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与SVF312R3K1CKU2R相关器件

型号	品牌	获取价格	描述	数据表
SVF312R3K1CKU4R	NXP	获取价格	Standard JTAG
SVF312R3K1CMK2R	NXP	获取价格	Standard JTAG
SVF312R3K1CMK4R	NXP	获取价格	Standard JTAG
SVF312R3K2CKU2	NXP	获取价格	Standard JTAG
SVF312R3K2CKU2R	NXP	获取价格	Standard JTAG
SVF312R3K2CKU4R	NXP	获取价格	Standard JTAG
SVF312R3K2CMK2R	NXP	获取价格	Standard JTAG
SVF312R3K2CMK4R	NXP	获取价格	Standard JTAG
SVF312R3N2CKU2	NXP	获取价格	Standard JTAG
SVF312R3N2CKU2R	NXP	获取价格	Standard JTAG

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