Datasheet > STPC0310BTI3

STPC0310BTI3

更新时间： 2024-11-24 22:50:03

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		微处理器 PC
页数	文件大小	规格书
51页	726K
描述
PC Compatible Embeded Microprocessor

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数据手册

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STPC0310BTI3 数据手册

STPC CONSUMER

PC Compatible Embeded Microprocessor

■

POWERFUL X86 PROCESSOR

64-BIT BUS ARCHITECTURE

64-BIT DRAM CONTROLLER

SVGA GRAPHICS CONTROLLER

UMA ARCHITECTURE

VIDEO SCALER

DIGITAL PAL/NTSC ENCODER

VIDEO INPUT PORT

CRT CONTROLLER

135MHz RAMDAC

PBGA388

3 LINE FLICKER FILTER

SCAN CONVERTER

PCI MASTER / SLAVE / ARBITER CTRL

ISA MASTER/SLAVE INTERFACE

IDE CONTROLLER

Figure 1. Logic Diagram

ISABUS

DMA CONTROLLER

x86

Core

INTERRUPT CONTROLLER

TIMER / COUNTERS

ISA

m/s

IPC

Host I/F

POWER MANAGEMENT

EIDE

PCI

m/s

EIDE

STPC CONSUMER OVERVIEW

PCI BUS

The STPC Consumer integrates a standard 5th

generation x86 core, a DRAM controller, a graph-

ics subsystem, a video pipeline and support logic

including PCI, ISA and IDE controllers to provide a

single Consumer orientated PC compatible sub-

system on a single device.

PCI

m/s

CCIRInput

TV Output

VIP

Digital

PAL/

The device is based on a tightly coupled Unified

Memory Architecture (UMA), sharing the same

memory array between the CPU main memory

and the graphics and video frame buffers.

Extra facilities are implemented to handle video

streams. Features include smooth scaling and

color space conversion of the video input stream

and mixing with graphics data. The chip also in-

cludes a built-in digital TV encoder and anti-flicker

filters that allow stable, high-quality display on

standard PAL or NTSC television sets without ad-

ditional components.

NTSC

AntiFlicker

Color Space

Converter

Video

pipeline

Color

Key

Chroma

Key

Monitor

SVGA

HW Cursor

CRTC

SYNCOutput

DRAM

CTRL

The STPC Consumer is packaged in a 388 Plastic

Ball Grid Array (PBGA).

8/2/00

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Issue 1.2

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