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STM32U575AI PDF预览

STM32U575AI

更新时间: 2024-11-06 14:57:15
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意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
338页 7080K
描述
Ultra-low-power with FPU Arm Cortex-M33 MCU with TrustZone, 160 MHz with 2 Mbytes of Flash memory

STM32U575AI 数据手册

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STM32U575xx  
Ultra-low-power Arm® Cortex®-M33 32-bit MCU+TrustZone®+FPU,  
240 DMIPS, up to 2 MB Flash memory, 786 KB SRAM  
Datasheet - production data  
Features  
Includes ST state-of-the-art patented  
technology  
UFBGA132  
(7 x 7 mm)  
UFBGA169  
(7 x 7 mm)  
LQFP48 (7 x 7 mm) UFQFPN48  
LQFP64 (10 x 10 mm) (7 x 7 mm)  
LQFP100 (14 x 14 mm)  
WLCSP90  
(4.2 x 3.95 mm)  
Ultra-low-power with FlexPowerControl  
1.71 V to 3.6 V power supply  
LQFP144 (20 x 20 mm)  
®
®
651 CoreMark (4.07 CoreMark /MHz)  
450 ULPMark™-CP  
–40 °C to +85/125 °C temperature range  
Low-power background autonomous mode  
(LPBAM): autonomous peripherals with DMA,  
functional down to Stop 2 mode  
109 ULPMark™-PP  
51.5 ULPMark™-CM  
V  
mode: supply for RTC, 32 x 32-bit backup  
BAT  
133000 SecureMark™-TLS  
registers and 2-Kbyte backup SRAM  
160 nA Shutdown mode (24 wake-up pins)  
210 nA Standby mode (24 wake-up pins)  
530 nA Standby mode with RTC  
Memories  
2-Mbyte flash memory with ECC, 2 banks  
read-while-write, including 512 Kbytes with  
100 kcycles  
1.9 μA Stop 3 mode with 16-Kbyte SRAM  
4.3 µA Stop 3 mode with full SRAM  
4.0 µA Stop 2 mode with 16-Kbyte SRAM  
8.95 µA Stop 2 mode with full SRAM  
19.5 μA/MHz Run mode @ 3.3 V  
786-Kbyte SRAM with ECC OFF or 722-Kbyte  
SRAM including up to 322-Kbyte SRAM with  
ECC ON  
External memory interface supporting SRAM,  
PSRAM, NOR, NAND, and FRAM memories  
2 Octo-SPI memory interfaces  
Core  
®
®
Security  
Arm 32-bit Cortex -M33 CPU with  
®
®
®
TrustZone , MPU, DSP, and FPU  
Arm TrustZone and securable I/Os,  
memories, and peripherals  
ART Accelerator  
Flexible life cycle scheme with RDP and  
8-Kbyte instruction cache allowing 0-wait-state  
execution from flash and external memories:  
up to 160 MHz, 240 DMIPS  
password protected debug  
Root of trust thanks to unique boot entry and  
secure hide protection area (HDP)  
4-Kbyte data cache for external memories  
Secure firmware installation (SFI) thanks to  
embedded root secure services (RSS)  
Power management  
Secure firmware upgrade support with TF-M  
HASH hardware accelerator  
Embedded regulator (LDO) and SMPS  
step-down converter supporting switch  
on-the-fly and voltage scaling  
True random number generator, NIST  
SP800-90B compliant  
Benchmarks  
96-bit unique ID  
1.5 DMIPS/MHz (Drystone 2.1)  
August 2023  
DS13737 Rev 8  
1/338  
This is information on a product in full production.  
www.st.com  

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