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STM32G474VEI3TR

更新时间： 2024-11-05 02:25:47
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 静态存储器
页数 文件大小 规格书
236页 3039K
描述
Arm® Cortex®-M4 32-bit MCUFPU, 170 MHz / 213 DMIPS, 128 KB SRAM, rich analog, math acc, 184 ps 12 chan Hi-res timer

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STM32G474VEI3TR 数据手册

 浏览型号STM32G474VEI3TR的Datasheet PDF文件第2页浏览型号STM32G474VEI3TR的Datasheet PDF文件第3页浏览型号STM32G474VEI3TR的Datasheet PDF文件第4页浏览型号STM32G474VEI3TR的Datasheet PDF文件第5页浏览型号STM32G474VEI3TR的Datasheet PDF文件第6页浏览型号STM32G474VEI3TR的Datasheet PDF文件第7页 
STM32G474xB STM32G474xC  
STM32G474xE  
Arm® Cortex®-M4 32-bit MCU+FPU, 170 MHz / 213 DMIPS,  
128 KB SRAM, rich analog, math acc, 184 ps 12 chan Hi-res timer  
Datasheet - production data  
Features  
®
®
• Core: Arm 32-bit Cortex -M4 CPU with FPU,  
Adaptive real-time accelerator (ART  
Accelerator) allowing 0-wait-state execution  
from Flash memory, frequency up to 170 MHz  
with 213 DMIPS, MPU, DSP instructions  
LQFP48 (7 x 7 mm)  
WLCSP81  
(4.02 x 4.27 mm)  
UFQFPN48  
(7 x 7 mm)  
LQFP64 (10 x 10 mm)  
LQFP80 (12 x 12 mm)  
LQFP100 (14 x 14 mm)  
LQFP128 (14 x 14 mm)  
• Operating conditions:  
– V , V  
voltage range:  
DD  
DDA  
UFBGA121  
(6 x 6 mm)  
TFBGA100  
(8 x 8 mm)  
1.71 V to 3.6 V  
• Mathematical hardware accelerators  
– CORDIC for trigonometric functions  
acceleration  
– Internal 32 kHz RC oscillator (± 5%)  
• Up to 107 fast I/Os  
– FMAC: filter mathematical accelerator  
– All mappable on external interrupt vectors  
• Memories  
– Several I/Os with 5 V tolerant capability  
– 512 Kbytes of Flash memory with ECC  
support, two banks read-while-write,  
proprietary code readout protection  
(PCROP), securable memory area, 1 Kbyte  
OTP  
• Interconnect matrix  
• 16-channel DMA controller  
• 5 x 12-bit ADCs 0.25 µs, up to 42 channels.  
Resolution up to 16-bit with hardware  
– 96 Kbytes of SRAM, with hardware parity  
check implemented on the first 32 Kbytes  
oversampling, 0 to 3.6 V conversion range  
• 7 x 12-bit DAC channels  
– Routine booster: 32 Kbytes of SRAM on  
instruction and data bus, with hardware  
parity check (CCM SRAM)  
– 3 x buffered external channels 1 MSPS  
– 4 x unbuffered internal channels 15 MSPS  
– External memory interface for static  
memories FSMC supporting SRAM,  
PSRAM, NOR and NAND memories  
• 7 x ultra-fast rail-to-rail analog comparators  
• 6 x operational amplifiers that can be used in  
PGA mode, all terminals accessible  
– Quad-SPI memory interface  
• Internal voltage reference buffer (VREFBUF)  
supporting three output voltages (2.048 V,  
2.5 V, 2.95 V)  
• Reset and supply management  
– Power-on/power-down reset  
(POR/PDR/BOR)  
• 17 timers:  
– Programmable voltage detector (PVD)  
– HRTIM (Hi-Resolution and complex  
waveform builder): 6 x16-bit counters,  
184 ps resolution, 12 PWM  
– Low-power modes: sleep, stop, standby  
and shutdown  
– V  
supply for RTC and backup registers  
BAT  
– 2 x 32-bit timer and 2 x 16-bit timers with  
up to four IC/OC/PWM or pulse counter  
and quadrature (incremental) encoder input  
• Clock management  
– 4 to 48 MHz crystal oscillator  
– 32 kHz oscillator with calibration  
– Internal 16 MHz RC with PLL option (± 1%)  
– 3 x 16-bit 8-channel advanced motor  
control timers, with up to 8 x PWM  
October 2020  
DS12288 Rev 5  
1/236  
This is information on a product in full production.  
www.st.com  
1234567...236

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