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STM32F407VE PDF预览

STM32F407VE

更新时间: 2022-06-26 11:43:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 闪存
页数 文件大小 规格书
185页 5432K
描述
ARM Cortex-M4 32b MCUFPU, 210DMIPS, up to 1MB Flash/1924KB RAM, USB OTG HS/FS

STM32F407VE 数据手册

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STM32F405xx, STM32F407xx  
Revision history  
Table 98. Document revision history (continued)  
Revision Changes  
Date  
Updated Figure 5: STM32F40x block diagram and Figure 7: Power  
supply supervisor interconnection with internal reset OFF  
Added SDIO, added notes related to FSMC and SPI/I2S in Table 2:  
STM32F405xx and STM32F407xx: features and peripheral counts.  
Starting from Silicon revision Z, USB OTG full-speed interface is now  
available for all STM32F405xx devices.  
Added full information on WLCSP90 package together with  
corresponding part numbers.  
Changed number of AHB buses to 3.  
Modified available Flash memory sizes in Section 2.2.4: Embedded  
Flash memory.  
Modified number of maskable interrupt channels in Section 2.2.10:  
Nested vectored interrupt controller (NVIC).  
Updated case of Regulator ON/internal reset ON, Regulator  
ON/internal reset OFF, and Regulator OFF/internal reset ON in  
Section 2.2.16: Voltage regulator.  
Updated standby mode description in Section 2.2.19: Low-power  
modes.  
Added Note 1 below Figure 16: STM32F40x UFBGA176 ballout.  
Added Note 1 below Figure 17: STM32F40x WLCSP90 ballout.  
Updated Table 7: STM32F40x pin and ball definitions.  
Added Table 8: FSMC pin definition.  
31-May-2012  
3
Removed OTG_HS_INTN alternate function in Table 7: STM32F40x  
pin and ball definitions and Table 9: Alternate function mapping.  
Removed I2S2_WS on PB6/AF5 in Table 9: Alternate function  
mapping.  
Replaced JTRST by NJTRST, removed ETH_RMII _TX_CLK, and  
modified I2S3ext_SD on PC11 in Table 9: Alternate function mapping.  
Added Table 10: STM32F40x register boundary addresses.  
Updated Figure 18: STM32F40x memory map.  
Updated VDDA and VREF+ decoupling capacitor in Figure 21: Power  
supply scheme.  
Added power dissipation maximum value for WLCSP90 in Table 14:  
General operating conditions.  
Updated VPOR/PDR in Table 19: Embedded reset and power control  
block characteristics.  
Updated notes in Table 21: Typical and maximum current consumption  
in Run mode, code with data processing running from Flash memory  
(ART accelerator disabled), Table 20: Typical and maximum current  
consumption in Run mode, code with data processing running from  
Flash memory (ART accelerator enabled) or RAM, and Table 22:  
Typical and maximum current consumption in Sleep mode.  
Updated maximum current consumption at TA = 25 °n Table 23:  
Typical and maximum current consumptions in Stop mode.  
DocID022152 Rev 4  
179/185  

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