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STLVD111_07 PDF预览

STLVD111_07

更新时间: 2024-11-16 03:30:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 时钟驱动器
页数 文件大小 规格书
19页 288K
描述
Programmable low voltage 1:10 differential LVDS clock driver

STLVD111_07 数据手册

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STLVD111  
Programmable low voltage  
1:10 differential LVDS clock driver  
Features  
100ps part-to part skew  
50ps bank skew  
Differential design  
Meets LVDS spec. for driver outputs and  
receiver inputs  
Reference voltage available output V  
BB  
TQFP32  
Low voltage V range of 2.375V to 2.625V  
CC  
High signalling rate capability (exceeds  
622MHz)  
Support open, short and terminated input fail-  
safe (low output state)  
STLVD111 is specifically designed, modelled and  
produced with low skew as the key goal. Optimal  
design and layout serve to minimize gate to gate  
skew within a device. The net result is a  
Programmable drivers power off control  
Description  
dependable guaranteed low skew device.  
The STLVD111 is a low skew programmable 1 to  
10 differential LVDS driver, designed for clock  
distribution. The select signal is fanned out to 10  
identical differential outputs.  
The STLVD111 can be used for high performance  
clock distribution in 2.5V systems with LVDS  
levels. Designers can take advantage of the  
device’s performance to distribute low skew  
clocks across the backplane or the board.  
The STLVD111 is provided with a 11 bit shift  
register with a serial in and a Control Register.  
The purpose is to enable or power off each output  
clock channel and to select the clock input. The  
Order codes  
Temperature  
Part number  
range  
Package  
Packaging  
STLVD111BFR  
-40 to 85 °C  
TQFP32 (Tape & Reel)  
Rev. 8  
2400 parts per reel  
May 2007  
1/19  
www.st.com  
19  

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