STLVD210BFR

更新时间： 2024-11-15 22:35:15

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		时钟驱动器
页数	文件大小	规格书
9页	158K
描述
DIFFERENTIAL LVDS CLOCK DRIVER

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中文翻译

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数据手册

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STLVD210BFR 数据手册

STLVD210

DIFFERENTIAL LVDS CLOCK DRIVER

■

100ps PART-TO-PART SKEW

50ps BANK SKEW

DIFFERENTIAL DESIGN

MEETS LVDS SPEC. FOR DRIVER

OUTPUTS AND RECEIVER INPUTS

REFERENCE VOLTAGE AVAILABLE

■

OUTPUT V

LOW VOLTAGE V RANGE OF 2.375V TO

2.625V

HIGH SIGNALLING RATE CAPABILITY

(EXCEEDS 700MHz)

SUPPORT OPEN, SHORT, AND

TERMINATED INPUT FAIL-SAFE (LOW

OUTPUT STATE)

TQFP32

■

PROGRAMMABLE DRIVERS POWER OFF

CONTROL

DESCRIPTION

STLVD210 is specifically designed, modelled and

produced with low skew as the key goal. Optimal

design and layout serve to minimize gate to gate

skew within a device. The net result is a

dependable guaranteed low skew device.

The STLVD210 can be used for high performance

clock distribution in 2.5V systems with LVDS

levels. Designers can be take advantage of the

device’s performance to distribute low skew

clocks across the backplane or the board.

The STLVD210 is a low skew programmable

1-to-5 dual differential LVDS driver, designed with

clock distribution in mind. The LVDS input signals

can be either differential or single-ended if the

VBB output is used.

The STLVD210 is provided with a 11 bit shift

The purpose is to enable or power off each output

clock channel and to select the clock input. The

ORDERING CODES

Temperature

Type

Package

Comments

Range

STLVD210BF

-40 to 85 °C

TQFP32 (Tray)

TQFP32 (Tape & Reel)

250 parts per Tray

2400 parts per reel

STLVD210BFR

December 2002

1/9

12 3 4 5 6 7...9

中文翻译

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