STK16C68
8K x 8 AutoStorePlus™ nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
DESCRIPTION
• Transparent Data Save on Power Down
• Internal Capacitor Guarantees AutoStore™
Regardless of Power-Down Slew Rate
• Nonvolatile Storage without Battery Problems
• Directly Replaces 8K x 8 Static RAM, Battery-
Backed RAM or EEPROM
• 20ns, 25ns, 35ns and 45ns Access Times
• STORE to EEPROM Initiated by Software or
AutoStorePlus™ on Power Down
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to EEPROM
• 100-Year Data Retention over Full Industrial
Temperature Range
• No Data Loss from Undershoot
• Commercial and Industrial Temperatures
• 28-Pin 600 mil PDIP and 350 mil SOIC Packages
The STK16C68 is a fast SRAM with a nonvolatile
EEPROM element incorporated in each static memory
cell. The SRAM can be read and written an unlimited
number of times, while independent nonvolatile data
resides in EEPROM. Data transfers from the SRAM to
the EEPROM (the STORE operation) can take place
automatically on power down. An internal capacitor
guarantees the STORE operation regardless of power-
down slew rate. Transfers from the EEPROM to the
SRAM (the RECALL operation) take place automatically
on restoration of power. Initiation of STORE and
RECALL cycles can also be controlled by entering con-
trol sequences on the SRAM inputs. The STK16C68 is
pin-compatible with 8k x 8 SRAMs and battery-backed
SRAMs, allowing direct substitution while enhancing
performance. The STK12C68, which uses an external
capacitor, and the STK15C68, which uses charge
stored in system capacitance, are alternatives for sys-
tems needing AutoStore™ operation.
PIN CONFIGURATIONS
BLOCK DIAGRAM
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
NC
A
A
A
A
A
A
A
A
A
DQ
DQ
DQ
2
12
EEPROM ARRAY
128 x 512
3
7
6
5
4
3
2
VCC
4
A
8
A
9
A5
5
6
A
STORE
11
G
A6
STORE/
RECALL
CONTROL
7
POWER
CONTROL
A7
8
A
E
10
STATIC RAM
ARRAY
9
RECALL
1
0
A8
10
11
12
13
14
DQ
DQ
7
6
5
128 x 512
A9
0
DQ
1
2
INTERNAL
CAPACITOR
28 - 600 PDIP
28 - 350 SOIC*
A11
A12
DQ
DQ
4
3
V
SS
*see order info
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
PIN NAMES
COLUMN I/O
SOFTWARE
DETECT
A0 - A12
A
- A
12
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 5V)
Ground
COLUMN DEC
0
W
DQ - DQ
0
7
A0 A1 A2 A3 A4 A10
G
E
G
E
V
W
CC
V
SS
July 1999
4-73