Datasheet > STK14C88-CF45ITR

STK14C88-CF45ITR

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
SIMTEK		存储静态存储器
页数	文件大小	规格书
19页	399K
描述
32Kx8 AutoStore nvSRAM

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中文翻译

获取价格

数据手册

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STK14C88-CF45ITR 数据手册

DATA VALID

STK14C88

SRAM WRITE CYCLES #1 & #2

(V = 5.0V 10%)

SYMBOLS

NO.

STK14C88-25 STK14C88-35 STK14C88-45

PARAMETER

UNITS

Alt.

MIN

MAX

MIN

MAX

MIN

MAX

Write Cycle Time

Write Pulse Width

AVAV

WLWH

WLEH

Chip Enable to End of Write

Data Set-up to End of Write

Data Hold after End of Write

Address Set-up to End of Write

Address Set-up to Start of Write

Address Hold after End of Write

Write Enable to Output Disable

Output Active after End of Write

ELWH

DVWH

WHDX

ELEH

DVEH

EHDX

AVWH

AVEH

AVWL

AVEL

WHAX

i, j

EHAX

WLQZ

WHQX

Note j: If W is low when E goes low, the outputs remain in the high-impedance state.

Note k: E or W must be ≥ V_IHduring address transitions.

Note l: HSB must be high during SRAM WRITE cycles.

k, l

SRAM WRITE CYCLE #1: W Controlled

AVAV

ADDRESS

WHAX

ELWH

AVWH

AVWL

WLWH

DATA IN

DVWH

WHDX

WLQZ

WHQX

HIGH IMPEDANCE

DATA OUT

PREVIOUS DATA

k, l

SRAM WRITE CYCLE #2: E Controlled

AVAV

ADDRESS

AVEL

ELEH

EHAX

AVEH

WLEH

DVEH

EHDX

DATA IN

DATA VALID

HIGH IMPEDANCE

DATA OUT

Rev 0.3

Document Control #ML0014

February 2007

1 2 3 456 7 8...19

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