Datasheet > STK14C88-CF25I

STK14C88-CF25I

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
SIMTEK		存储静态存储器
页数	文件大小	规格书
19页	399K
描述
32Kx8 AutoStore nvSRAM

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数据手册

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STK14C88-CF25I 数据手册

STK14C88

SRAM READ CYCLES #1 & #2

(V = 5.0V 10%)

SYMBOLS

STK14C88-25

STK14C88-35

STK14C88-45

NO.

PARAMETER

UNITS

#1, #2

Alt.

MIN

MAX

MIN

MAX

MIN

MAX

Chip Enable Access Time

ELQV

ACS

Read Cycle Time

AVAV

Address Access Time

AVQV

Output Enable to Data Valid

Output Hold after Address Change

Chip Enable to Output Active

Chip Disable to Output Inactive

Output Enable to Output Active

Output Disable to Output Inactive

Chip Enable to Power Active

Chip Disable to Power Standby

GLQV

AXQX

ELQX

EHQZ

GLQX

OLZ

OHZ

GHQZ

ELICCH

EHICCL

Note g: W and HSB must be high during SRAM READ cycles and low during SRAM WRITE cycles.

Note h: I/O state assumes E and G < V and W > V ; device is continuously selected.

Note i: Measured 200mV from steady state output voltage.

g, h

SRAM READ CYCLE #1: Address Controlled

AVAV

ADDRESS

AVQV

AXQX

DQ (DATA OUT)

DATA VALID

SRAM READ CYCLE #2: E Controlled

AVAV

ADDRESS

ELQV

EHICCL

ELQX

EHQZ

GLQV

GHQZ

GLQX

DATA VALID

DQ (DATA OUT)

ELICCH

ACTIVE

STANDBY

Rev 0.3

Document Control #ML0014

February, 2007

1 2 345 6 7...19

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