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STK11C88-P20 PDF预览

STK11C88-P20

更新时间: 2024-11-07 22:24:59
品牌 Logo 应用领域
其他 - ETC 内存集成电路静态存储器光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
9页 93K
描述
32K x 8 nvSRAM QUANTUM TRAP CMOS NONVOLATILE STATIC RAM

STK11C88-P20 数据手册

 浏览型号STK11C88-P20的Datasheet PDF文件第2页浏览型号STK11C88-P20的Datasheet PDF文件第3页浏览型号STK11C88-P20的Datasheet PDF文件第4页浏览型号STK11C88-P20的Datasheet PDF文件第5页浏览型号STK11C88-P20的Datasheet PDF文件第6页浏览型号STK11C88-P20的Datasheet PDF文件第7页 
STK11C88  
32K x 8 nvSRAM  
QuantumTrap™ CMOS  
Nonvolatile Static RAM  
FEATURES  
DESCRIPTION  
20ns, 25ns, 35ns and 45ns Access Times  
STORE to EEPROM Initiated by Software  
The Simtek STK11C88 is a fast static RAM with a  
nonvolatile, electrically erasable PROM element  
incorporated in each static memory cell. The SRAM  
can be read and written an unlimited number of  
times, while independent nonvolatile data resides in  
EEPROM. Data transfers from the SRAM to the  
EEPROM (the STORE operation), or from EEPROM to  
SRAM (the RECALL operation), take place using a  
software sequence. Transfers from the EEPROM to  
the SRAM (the RECALL operation) also take place  
automatically on restoration of power.  
RECALL to SRAM Initiated by Software or  
Power Restore  
10mA Typical ICC at 200ns Cycle Time  
Unlimited READ, WRITE and RECALL Cycles  
1,000,000 STORE Cycles to EEPROM  
100-Year Data Retention in EEPROM  
Commercial and Industrial Temperatures  
28-Pin PDIP and SOIC Packages  
The STK11C88 is pin-compatible with industry-  
standard SRAMs.  
BLOCK DIAGRAM  
PIN CONFIGURATIONS  
A
A
A
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
CC  
W
14  
EEPROM ARRAY  
2
12  
512 x 512  
3
A
A
A
A
7
6
5
4
3
2
13  
8
A5  
A6  
A7  
A8  
A
4
A
A
A
A
A
A
DQ  
DQ  
DQ  
5
9
STORE  
STORE/  
RECALL  
CONTROL  
6
11  
7
G
STATIC RAM  
ARRAY  
8
A
E
10  
RECALL  
A9  
9
1
0
A11  
A12  
A13  
A14  
512 x 512  
10  
11  
12  
13  
14  
DQ  
DQ  
7
6
5
28 - 300 PDIP  
28 - 600 PDIP  
28 - 300 SOIC  
28 - 350 SOIC  
0
DQ  
1
DQ  
DQ  
2
4
3
SOFTWARE  
DETECT  
A0 - A13  
V
SS  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
COLUMN I/O  
PIN NAMES  
COLUMN DEC  
A
- A  
Address Inputs  
Write Enable  
Data In/Out  
Chip Enable  
Output Enable  
Power (+5V)  
Ground  
0
14  
W
A0 A1 A2 A3 A4A10  
DQ - DQ  
0
7
G
E
E
G
W
V
V
CC  
SS  
July 1999  
5-1  

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