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STK11C68-S45 PDF预览

STK11C68-S45

更新时间: 2024-11-07 22:53:23
品牌 Logo 应用领域
其他 - ETC 内存集成电路静态存储器光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
10页 61K
描述
8K x 8 nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM

STK11C68-S45 数据手册

 浏览型号STK11C68-S45的Datasheet PDF文件第2页浏览型号STK11C68-S45的Datasheet PDF文件第3页浏览型号STK11C68-S45的Datasheet PDF文件第4页浏览型号STK11C68-S45的Datasheet PDF文件第5页浏览型号STK11C68-S45的Datasheet PDF文件第6页浏览型号STK11C68-S45的Datasheet PDF文件第7页 
STK11C68  
8K x 8 nvSRAM  
QuantumTrap™ CMOS  
Nonvolatile Static RAM  
FEATURES  
DESCRIPTION  
• 20ns, 25ns, 35ns and 45ns Access Times  
The Simtek STK11C68 is a fast static RAM with a  
nonvolatile, electrically erasable PROM element  
incorporated in each static memory cell. The SRAM  
can be read and written an unlimited number of  
times, while independent nonvolatile data resides in  
the EEPROM. Data transfers from the SRAM to the  
EEPROM (the STORE operation), or from EEPROM to  
SRAM (the RECALL operation), take place using a  
software sequence. Transfers from the EEPROM to  
the SRAM (the RECALL operation) also take place  
automatically on restoration of power.  
STORE to EEPROM Initiated by Software  
RECALL to SRAM Initiated by Software or  
Power Restore  
• 10mA Typical ICC at 200ns Cycle Time  
• Unlimited READ, WRITE and RECALL Cycles  
• 1,000,000 STORE Cycles to EEPROM  
• 100-Year Data Retention over Full Industrial  
Temperature Range  
• Commercial and Industrial Temperatures  
• 28-Pin DIP and SOIC Packages  
The STK11C68 is pin-compatible with industry-  
standard SRAMs. MIL-STD-883 device is also  
available (STK11C68-M).  
BLOCK DIAGRAM  
PIN CONFIGURATIONS  
1
NC  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
CC  
W
NC  
EEPROM ARRAY  
128 x 512  
2
A
12  
3
A
7
6
5
4
3
A
A
A
5
4
A
A
8
5
A
A
A
A
A
9
STORE  
6
STORE/  
RECALL  
CONTROL  
6
A
11  
7
G
A
7
STATIC RAM  
ARRAY  
8
RECALL  
2
10  
A
8
9
A
E
1
0
128 x 512  
10  
11  
12  
13  
14  
A
A
A
A
DQ  
9
7
6
5
DQ  
DQ  
DQ  
0
28 - 300 PDIP  
28 - 300 CDIP  
28 - 350 SOIC  
11  
12  
DQ  
DQ  
1
DQ  
DQ  
2
4
3
SOFTWARE  
DETECT  
A
- A  
12  
0
V
SS  
DQ  
DQ  
DQ  
0
1
2
COLUMN I/O  
PIN NAMES  
COLUMN DEC  
DQ  
DQ  
DQ  
DQ  
DQ  
A
- A  
Address Inputs  
Write Enable  
Data In/Out  
Chip Enable  
Output Enable  
Power (+ 5V)  
Ground  
3
4
0
12  
W
5
6
7
A
A A  
A A  
A
1 4  
2 3  
10  
0
G
DQ - DQ  
0
7
E
E
G
W
V
CC  
SS  
V
June 1999  
4-21  

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