Very Low Power/Voltage CMOS SRAM
1M X 8 bit
STC
STC62WV1M8
FEATURES
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 30mA (@55ns) operating current
I -grade: 31mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
1.5uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 75mA (@55ns) operating current
I -grade: 76mA (@55ns) operating current
C-grade: 60mA (@70ns) operating current
I -grade: 61mA (@70ns) operating current
8.0uA (Typ.) CMOS standby current
GENERAL DESCRIPTION
The STC62WV1M8 is a high performance , very low power CMOS Static
Random Access Memory organized as 1,048,576 words by 8 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
1.5uA at 3V/25oC and maximum access time of 55ns at 3.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable(CE1)
, an active HIGH chip enable (CE2) and active LOW output enable (OE)
and three-state output drivers.
• High speed access time :
-55
-70
55ns
70ns
The STC62WV1M8 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
• Automatic power down when chip is deselected
The STC62WV1M8 is available in 48B BGA and 44L TSOP2 packages.
PRODUCT FAMILY
POWER DISSIPATION
SPEED
( ns )
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
( ICCSB1, Max )
( ICC, Max )
PKG TYPE
Vcc=5V
70ns
Vcc=3V
70ns
55ns : 3.0~5.5V
70ns : 2.7~5.5V
Vcc=3V
Vcc=5V
55uA
STC62WV1M8EC
STC62WV1M8FC
STC62WV1M8EI
STC62WV1M8FI
TSOP2-44
BGA-48-0912
TSOP2-44
+0O C to +70OC 2.4V ~ 5.5V
-40OC to +85OC 2.4V ~ 5.5V
55 / 70
55 / 70
5uA
24mA
25mA
60mA
10uA
110uA
61mA
BGA-48-0912
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CE1
NC
NC
DQ0
DQ1
VCC
GND
DQ2
DQ3
NC
NC
A5
A6
A7
OE
CE2
A8
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A13
A17
A15
A18
A16
A14
A12
A7
NC
DQ7
DQ6
GND
VCC
DQ5
DQ4
NC
STC62WV1M8EC
STC62WV1M8EI
Address
Input
Memory Array
22
2048
Row
2048 X 4096
Decoder
NC
A9
Buffer
WE
A19
A18
A17
A16
A15
A6
A5
A4
18
19
20
21
A10
A11
A12
A13
A14
22
4096
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
1
2
3
4
5
6
8
Column I/O
Write Driver
Sense Amp
A
B
C
D
E
F
OE
A0
A1
A2
CE2
NC
NC
NC
8
8
Data
Output
Buffer
NC
NC
A3
A5
A4
CE1
NC
512
A6
D0
D4
Column Decoder
18
VSS
A17
VCC
A7
VCC
VSS
D1
D2
D5
D6
CE1
CE2
WE
OE
Control
A16
A15
A13
A10
VCC
D3
Address Input Buffer
D7
NC
NC
NC
NC
WE
A11
A14
A12
A9
Vdd
Gnd
A11A9 A8 A3 A2 A1 A0A10 A19
G
H
NC
A18
A8
A19
48-ball BGA top view
STC International Limited. reserves the right to modify document contents without notice.
Revision 2.1
Jan. 2004
R0201-STC62WV1M8
1