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ST72F561J9TATXE PDF预览

ST72F561J9TATXE

更新时间： 2024-11-06 13:14:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
262页 3876K
描述
IC,MICROCONTROLLER,8-BIT,ST72 CPU,CMOS,QFP,44PIN,PLASTIC

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中文翻译

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ST72F561J9TATXE 技术参数

是否Rohs认证：符合生命周期：Obsolete
Reach Compliance Code：compliant风险等级：5.84
Is Samacsys：N位大小：8
CPU系列：ST72JESD-30 代码：S-PQFP-G44
端子数量：44片上程序ROM宽度：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP44,.47SQ,32封装形状：SQUARE
封装形式：FLATPACK电源：5 V
认证状态：Not QualifiedRAM（字节）：2048
ROM（单词）：61440ROM可编程性：FLASH
速度：8 MHz子类别：Microcontrollers
最大压摆率：15 mA标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
Base Number Matches：1

ST72F561J9TATXE 数据手册

 浏览型号ST72F561J9TATXE的Datasheet PDF文件第2页浏览型号ST72F561J9TATXE的Datasheet PDF文件第3页浏览型号ST72F561J9TATXE的Datasheet PDF文件第4页浏览型号ST72F561J9TATXE的Datasheet PDF文件第5页浏览型号ST72F561J9TATXE的Datasheet PDF文件第6页浏览型号ST72F561J9TATXE的Datasheet PDF文件第7页 
ST72561  
8-BIT MCU WITH FLASH OR ROM,  
10-BIT ADC, 5 TIMERS, SPI, LINSCI, ACTIVE CAN  
PRELIMINARY DATA  
ꢀ Memories  
– 32K to 60K High Density Flash (HDFlash) or  
ROM with read-out protection capability. In-  
Application Programming and In-Circuit Pro-  
gramming for HDFlash devices  
– 1 to 2K RAM  
– HDFlash endurance: 100 cycles, data reten-  
tion: 20 years at 55°C  
TQFP32  
7x7mm  
TQFP64  
14 x 14  
ꢀ Clock, Reset and Supply Management  
– Low power crystal/ceramic resonator oscilla-  
tors and bypass for external clock  
– PLL for 2x frequency multiplication  
– Five Power Saving Modes: Halt, Auto Wake  
TQFP44  
10x10mm  
TQFP64  
10 x 10  
Up From Halt, Active-Halt, Wait and Slow  
ꢀ Interrupt Management  
– Nested interrupt controller  
– Main Clock Controller with: Real time base  
and Clock output  
– Window watchdog timer  
– 14 interrupt vectors plus TRAP and RESET  
– TLI top level interrupt (on 64-pin devices)  
– Up to 21 external interrupt lines (on 4 vectors)  
ꢀ Up to 48 I/O Ports  
ꢀ Up to 4 Communications Interfaces  
– SPI synchronous serial interface  
– Up to 48 multifunctional bidirectional I/O lines  
– Up to 36 alternate function lines  
– Up to 6 high sink outputs  
– Master/slave LINSCIasynchronous serial  
interface  
– Master-only LINSCIasynchronous serial in-  
terface  
ꢀ 5 Timers  
– CAN 2.0B active  
ꢀ Analog peripheral (low current coupling)  
– 16-bit Timer with: 2 input captures, 2 output  
compares, external clock input, PWM and  
pulse generator modes  
– 8-bit Timer with: 1 or 2 input captures, 1 or 2  
output compares, PWM and pulse generator  
modes  
– 10-bit A/D Converter with up to 16 inputs  
– Up to 9 robust ports (low current coupling)  
ꢀ Instruction Set  
– 8-bit PWM Auto-Reload Timer with: 1 or 2 in-  
put captures, 2 or 4 independent PWM output  
channels, output compare and time base in-  
terrupt, external clock with event detector  
– 8-bit data manipulation  
– 63 basic instructions  
– 17 main addressing modes  
– 8 x 8 unsigned multiply instruction  
ꢀ Development Tools  
– Full hardware/software development package  
Device Summary  
Features  
ST72(F)561(AR/R/J/K)9  
ST72(F)561(AR/R/J/K)6  
Program memory - bytes  
RAM (stack) - bytes  
Operating Supply  
CPU Frequency  
60K  
32K  
1K (256)  
2K (256)  
4.5V to 5.5V  
External Resonator Osc. w/ PLLx2/8MHz  
-40°C to +125°C  
TQFP64 10x10mm (AR), TQFP64 14x14mm (R), TQFP44 10x10mm (J), TQFP32 7x7mm (K)  
Max. Temp. Range  
Packages  
Rev. 2  
1/262  
May 2004  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without1notice.  
1234567...262

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