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ST72325K9T3 PDF预览

ST72325K9T3

更新时间: 2022-03-04 06:14:25
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意法半导体 - STMICROELECTRONICS 闪存
页数 文件大小 规格书
197页 3877K
描述
8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface

ST72325K9T3 数据手册

 浏览型号ST72325K9T3的Datasheet PDF文件第4页浏览型号ST72325K9T3的Datasheet PDF文件第5页浏览型号ST72325K9T3的Datasheet PDF文件第6页浏览型号ST72325K9T3的Datasheet PDF文件第8页浏览型号ST72325K9T3的Datasheet PDF文件第9页浏览型号ST72325K9T3的Datasheet PDF文件第10页 
ST72325xx  
HALT mode when the application is in idle or  
stand-by state.  
1 DESCRIPTION  
The ST72F325 Flash and ST72325 ROM devices  
are members of the ST7 microcontroller family de-  
signed for mid-range applications.  
Typical applications are consumer, home, office  
and industrial products.  
The devices feature an on-chip Debug Module  
(DM) to support in-circuit debugging (ICD). For a  
description of the DM registers, refer to the ST7  
ICC Protocol Reference Manual.  
They are derivatives of the ST72321 and ST72324  
devices, with enhanced characteristics and robust  
Clock Security System.  
All devices are based on a common industry-  
standard 8-bit core, featuring an enhanced instruc-  
tion set and are available with Flash or ROM pro-  
gram memory. The ST7 family architecture offers  
both power and flexibility to software developers,  
enabling the design of highly efficient and compact  
application code.  
Main Differences with ST72321:  
– LQFP48 and LQFP32 packages  
– Clock Security System  
– Internal RC, Readout protection, LVD and PLL  
without limitations  
– Negative current injection not allowed on I/O port  
PB0 (instead of PC6).  
The on-chip peripherals include an A/D converter,  
a PWM Autoreload timer, 2 general purpose tim-  
2
ers, I C bus, SPI interface and an SCI interface.  
– External interrupts have Exit from Active Halt  
mode capability.  
For power economy, microcontroller can switch  
dynamically into WAIT, SLOW, ACTIVE-HALT or  
Figure 1. Device Block Diagram  
8-BIT CORE  
ALU  
PROGRAM  
MEMORY  
(16K - 60K Bytes )  
1)  
RESET  
CONTROL  
V
PP  
RAM  
TLI  
1)  
(512 - 2048 Bytes )  
V
SS  
DD  
LVD  
AVD  
OSC  
V
EVD  
WATCHDOG  
OSC1  
OSC2  
DEBUG MODULE  
MCC/RTC/BEEP  
I2C  
PA7:0  
(8 bits on AR devices)  
PORT F  
TIMER A  
BEEP  
PORT A  
(5 bits on C/J devices)  
(4 bits on K devices)  
PF7:0  
(8 bits on AR devices)  
(6 bits on C/J devices)  
(5 bits on K devices)  
PORT B  
PB7:0  
(8 bits on AR devices)  
(5 bits on C/J devices)  
(3 bits on K devices)  
PWM ART  
PORT E  
PE7:0  
PORT C  
TIMER B  
SPI  
(8 bits on AR devices)  
(2 bits on C/J/K devices)  
SCI  
PC7:0  
(8 bits)  
PORT D  
PD7:0  
(8 bits on AR devices)  
(6 bits on C/J devices)  
(2 bits on K devices)  
10-BIT ADC  
V
AREF  
V
SSA  
1)  
ROM devices have up to 32 Kbytes of program memory and up to 1 Kbyte of RAM.  
7/197  

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