Datasheet > SSTVF16859BS,118

SSTVF16859BS,118

更新时间： 2024-11-16 15:52:59

品牌	Logo	应用领域
恩智浦 - NXP		输出元件逻辑集成电路触发器电视
页数	文件大小	规格书
23页	134K
描述
IC SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC56, 8 X 8 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-684-1, HVQFN-56, FF/Latch

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SSTVF16859BS,118 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFN	包装说明：	HVQCCN,
针数：	56	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.16
系列：	SSTV	JESD-30 代码：	S-PQCC-N56
JESD-609代码：	e4	长度：	8 mm
逻辑集成电路类型：	D FLIP-FLOP	湿度敏感等级：	1
位数：	13	功能数量：	1
端子数量：	56	最高工作温度：	70 °C
最低工作温度：		输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	传播延迟（tpd）：	2.5 ns
认证状态：	Not Qualified	座面最大高度：	1 mm
最大供电电压 (Vsup)：	2.7 V	最小供电电压 (Vsup)：	2.3 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	NICKEL PALLADIUM GOLD
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
触发器类型：	POSITIVE EDGE	宽度：	8 mm
最小 fmax：	210 MHz	Base Number Matches：	1

SSTVF16859BS,118 数据手册

SSTVF16859

13-bit 1 : 2 SSTL_2 registered buffer for DDR

Rev. 02 — 19 July 2005

Product data sheet

1. General description

The SSTVF16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock

inputs, designed to operate between 2.3 V and 2.7 V for PC1600-PC2700 applications or

between 2.5 V and 2.7 V for PC3200 applications. All inputs are compatible with the

JEDEC standard for SSTL_2 with V_refnormally at 0.5 × V_DD, except the LVCMOS reset

(RESET) input. All outputs are SSTL_2, Class II compatible, which can be used for

standard stub-series applications or capacitive loads. Master reset (RESET)

asynchronously resets all registers to zero.

The SSTVF16859 is intended to be incorporated into standard DIMM (Dual In-Line

Memory Module) designs deﬁned by JEDEC, such as DDR (Double Data Rate) SDRAM

and SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM

transfers data on both clock edges (rising and falling), thus doubling the peak bus

bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz.

The device data inputs consist of different receivers. One differential input is tied to the

input pin while the other is tied to a reference input pad, which is shared by all inputs.

The clock input is fully differential (CK and CK) to be compatible with DRAM devices that

are installed on the DIMM. Data are registered at the crossing of CK going HIGH, and CK

going LOW. However, since the control inputs to the SDRAM change at only half the data

rate, the device must only change state on the positive transition of the CK signal. In order

to be able to provide deﬁned outputs from the device even before a stable clock has been

supplied, the device has an asynchronous input pin (RESET), which when held to the

LOW state, resets all registers and all outputs to the LOW state.

The device supports low-power standby operation. When RESET is LOW, the differential

input receivers are disabled, and un-driven (ﬂoating) data, clock, and reference voltage

(VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset, and

all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid

logic HIGH or LOW level.

To ensure deﬁned outputs from the register before a stable clock has been supplied,

RESET must be held in the LOW state during power-up.

In the DDR DIMM application, RESET is speciﬁed to be completely asynchronous with

respect to CK and CK. Therefore, no timing relationship can be guaranteed between the

two. When entering RESET, the register will be cleared and the outputs will be driven

LOW. As long as the data inputs are LOW, and the clock is stable during the time from the

LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the outputs

will remain LOW.

12 3 4 5 6 7...23

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与SSTVF16859BS,118相关器件

型号	品牌	获取价格	描述	数据表
SSTVF16859BS,151	NXP	获取价格	IC SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC56, 8 X 8 MM, 0.85 M
SSTVF16859BS,157	NXP	获取价格	IC SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC56, 8 X 8 MM, 0.85 M
SSTVF16859DGG	NXP	获取价格	13-bit 1:2 SSTL_2 registered buffer for DDR
SSTVF16859EC	NXP	获取价格	13-bit 1:2 SSTL_2 registered buffer for DDR
SSTVF16859EC,518	NXP	获取价格	SSTVF16859 - 13-bit 1 : 2 SSTL_2 registered buffer for DDR
SSTVF16859EC,551	NXP	获取价格	SSTVF16859 - 13-bit 1 : 2 SSTL_2 registered buffer for DDR
SSTVF16859EC,557	NXP	获取价格	SSTVF16859 - 13-bit 1 : 2 SSTL_2 registered buffer for DDR
SSTVF16859YK-T	IDT	获取价格	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 13-Bit, True Output
SSTVN16857	FAIRCHILD	获取价格	14-Bit Register with SSTL-2 Compatible I/O and Reset
SSTVN16857MTD	FAIRCHILD	获取价格	14-Bit Register with SSTL-2 Compatible I/O and Reset

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