Datasheet > SS2625B-7.5

SS2625B-7.5

更新时间： 2024-01-22 08:16:11

品牌	Logo	应用领域
铁电 - RAMTRON		静态存储器内存集成电路
页数	文件大小	规格书
30页	223K
描述
ZBT SRAM, 2MX36, 4.2ns, CMOS, PBGA119, PLASTIC, BGA-119

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

SS2625B-7.5 技术参数

生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	,	针数：	119
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.84
最长访问时间：	4.2 ns	JESD-30 代码：	R-PBGA-B119
内存密度：	75497472 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	36	功能数量：	1
端子数量：	119	字数：	2097152 words
字数代码：	2000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	2MX36	封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	认证状态：	Not Qualified
最大供电电压 (Vsup)：	2.625 V	最小供电电压 (Vsup)：	2.375 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子位置：	BOTTOM
Base Number Matches：	1

SS2625B-7.5 数据手册

72Mbit Pipelined BSRAM

w/ NoBL Architecture

2Mx36

Preliminary Data Sheet

Pin Descriptions

Symbol

Type

Function

CLK

Input

Clock: All input signals (except G#) and output signals are referenced to the rising edge of CLK.

CKE#

Clock Enable: This active low input enables the internal clock signal. If CKE# is driven high, the chip

ignores the clock (all signals except G#) and suspends pending operations.

CE1#,

CE2,

CE3#

Input

Chip Enable Inputs: These inputs determine whether the RAM begins a read, write, or deselect

cycle. When qualified by LD# low, all three inputs must be true to select the chip and begin a read or

write cycle. When qualified by LD# low, at least one chip enable input must be false to begin a

deselect cycle.

LD#

Input

Load Input: This active low input loads the external address, and begins a new read or write cycle.

Once a read or write cycle is initiated, LD# must be negated to advance the internal burst counter.

LD# cannot be asserted for two consecutive clocks.

R/W#

Input

Read/Write Input: When LD# is asserted and the chip is enabled, this input determines whether the

chip begins a read (R/W# high) or write (R/W# low) cycle.

BW _[a:d]

Byte Write Inputs: These active low inputs allow write data to be written (BW_x# low) or masked

(BW_x# high) during write cycles. During read and deselect cycles, the BW_x# inputs are ignored.

BW_a# controls DQ_a, BW_b# controls DQ_b, BW_c# controls DQ_c, and BW_d# controls DQ_d.

A, A1, A0

DQ _[a:d]

Input

Address Inputs: Used to select a starting burst address location. The address inputs are sampled

when LD# is low and the chip is enabled. Inputs A1 and A0 determine the starting address for all

burst cycles.

Input/

Output

Data I/O Inputs: These pins deliver output data during burst read cycles. Output data is valid t_CO

from the rising edge of the clock. These data pins also allow input write data to be written to the

chip. Input data must satisfy setup and hold timing specifications.

Input

Output Enable Input: This active low input enables the output data buffers to drive output data

during read cycles. When negated, G# three states the data bus. The data output pins are

automatically three stated during write and deselect cycles.

LBO#

DNU

Linear Burst Order Input: This signal must remain in steady state.

Low – Linear burst.

High – Interleaved burst.

Do Not Use Input: These unused pins may be left open circuit, and should be reserved for future

address pins.

TCK

TMS

TDI

Input

Test Clock: Input clock for boundary scan. If boundary scan is not used, TCK must be tied to V_SS.

Test Mode Select: This input controls the TAP controller and is sampled on the rising edge of TCK.

Test Data In: This is the serial data input for boundary scan testing.

Test Data Out: This is the serial data output for boundary scan testing.

Core Power Supply: Connect to 3.3V or 2.5V.

Input

TDO

V_DD

Output

Supply

V_DDQ

V_SS,V_SSQ

I/O Power Supply: Connect to 3.3V (only on V_DD= 3.3V devices) or 2.5V.

Ground: V_SSand V_SSQare connected inside the chip.

No Connect: - These pins do not connect to the chip.

Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921

PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com

The information contained herein is subject to change without notice.

Page 4 of 30

Revision 1.0

1 2 345 6 7...30

下载PDF

与SS2625B-7.5相关器件

型号	品牌	描述	获取价格	数据表
SS2625Q-10	RAMTRON	ZBT SRAM, 2MX36, 5ns, CMOS, PQFP100, TQFP-100	获取价格
SS2625Q1-10	RAMTRON	ZBT SRAM, 2MX36, 5ns, CMOS, PQFP100, TQFP-100	获取价格
SS2625Q1-6	RAMTRON	ZBT SRAM, 2MX36, 3.5ns, CMOS, PQFP100, TQFP-100	获取价格
SS2625Q1-7.5	RAMTRON	ZBT SRAM, 2MX36, 4.2ns, CMOS, PQFP100, TQFP-100	获取价格
SS2625Q-6	RAMTRON	ZBT SRAM, 2MX36, 3.5ns, CMOS, PQFP100, TQFP-100	获取价格
SS2625Q-7.5	RAMTRON	ZBT SRAM, 2MX36, 4.2ns, CMOS, PQFP100, TQFP-100	获取价格

与SS2625B-7.5相关文章

STM32H743技术深度剖析与应用案例探索
2024-05-30

17
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
2024-05-30

16
74HC14芯片资料介绍：性能特性分析、引脚介绍
2024-05-30

14
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
2024-05-30

11

产品中心

服务支持

精选活动

关于我们

帮助中心

SS2625B-7.5

SS2625B-7.5 技术参数

SS2625B-7.5 数据手册

与SS2625B-7.5相关器件

与SS2625B-7.5相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SS2625B-7.5

SS2625B-7.5 技术参数

SS2625B-7.5 数据手册

与SS2625B-7.5相关器件

与SS2625B-7.5相关文章

您还可以找

您在本页遇到什么问题？