Datasheet > SS2625Q1-6

SS2625Q1-6

更新时间： 2024-02-21 04:45:46

品牌	Logo	应用领域
铁电 - RAMTRON		静态存储器内存集成电路
页数	文件大小	规格书
30页	223K
描述
ZBT SRAM, 2MX36, 3.5ns, CMOS, PQFP100, TQFP-100

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SS2625Q1-6 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFP,	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.84
最长访问时间：	3.5 ns	JESD-30 代码：	R-PQFP-G100
内存密度：	75497472 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	36	功能数量：	1
端子数量：	100	字数：	2097152 words
字数代码：	2000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	2MX36	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK	并行/串行：	PARALLEL
认证状态：	Not Qualified	最大供电电压 (Vsup)：	2.625 V
最小供电电压 (Vsup)：	2.375 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子位置：	QUAD	Base Number Matches：	1

SS2625Q1-6 数据手册

72Mbit Pipelined BSRAM

w/ NoBL Architecture

2Mx36

Preliminary Data Sheet

Description

Features

The Enhanced Memory Systems SS2625 is a 72-Mbit

synchronous pipelined burst SRAM designed specifically to

support back-to-back read/write operations without the

insertion of wait states. The device is organized as 2Mx36

and is offered in 3.3V and 2.5V versions. They are designed

to transfer data on every clock cycle. This feature

dramatically improves throughput, especially in systems that

require frequent write/read transitions.

•

High Density 72-Mbit

166 MHz bus operations with zero wait states –

Data is transferred on every clock

Fully Registered for Pipelined Operation

User Selectable Linear or Interleaved Burst Order

Byte Write Capability

•

Single 2.5V or 3.3V Power Supply

Fast Clock to Output Times

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

The clock input is qualified by the Clock Enable signal,

which, when deasserted, suspends operation and extends the

previous clock cycle. Maximum access delay from the rising

edge of the clock is 3.5 ns (166 MHz device).

•

3.5 ns (for 166 MHz device)

4.2 ns (for 133 MHz device)

5.0 ns (for 100 MHz device)

•

Clock Enable pin to Suspend Operations

Synchronous Self Timed Writes

Asynchronous Output Enable

JEDEC Standard 100-pin TQFP & 119-pin PBGA

Low Standby Power

JTAG 1149.1 Compliant Boundary Scan

Write operations are controlled by the four Byte Write Select

signals and a Read/Write signal. All writes are conducted

with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enable signals and an asynchronous

Output Enable signal provide for easy depth expansion and

output three-state control. To avoid bus contention, the output

drivers are synchronously three-stated during the data portion

of a write sequence.

Block Diagram

CLK

Data-In

Reg.

/CE

LD#

Addr

CKE#

CE1#

CE2

CE3#

R/W#

BW#(a:d)

2Mx36

CONTROL

and WRITE

LOGIC

Memory

Array

DQ(a:d)

This is a product in sampling or pre-production phase of development. Char-

acteristic data and other specifications are subject to change without notice.

Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921

PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com

Revision 1.0

Page 1 of 30

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