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SPXD3015VMM1R PDF预览

SPXD3015VMM1R

更新时间: 2024-10-28 11:59:23
品牌 Logo 应用领域
飞思卡尔 - FREESCALE 微控制器
页数 文件大小 规格书
139页 792K
描述
PXS30 Microcontroller

SPXD3015VMM1R 数据手册

 浏览型号SPXD3015VMM1R的Datasheet PDF文件第1页浏览型号SPXD3015VMM1R的Datasheet PDF文件第2页浏览型号SPXD3015VMM1R的Datasheet PDF文件第3页浏览型号SPXD3015VMM1R的Datasheet PDF文件第5页浏览型号SPXD3015VMM1R的Datasheet PDF文件第6页浏览型号SPXD3015VMM1R的Datasheet PDF文件第7页 
Introduction  
Table 1. PXS30 Family Feature Set (continued)  
Features  
PXS3010  
PXS3015  
PXS3020  
Clocking  
Clock monitor unit  
(CMU)  
3 modules  
Clock output  
2 modules  
Frequency-modulated  
phase-locked loop  
(FMPLL)  
2 modules (system and auxiliary)  
IRCOSC – 16 MHz  
1
1
XOSC 4 MHz – 40 MHz  
Supply  
Power management unit  
(PMU)  
Yes  
1.2 V low-voltage  
detector (LVD12)  
1
1
4
1.2 V high-voltage  
detector (HVD12)  
2.7 V low-voltage  
detector (LVD27)  
Debug  
Nexus  
Class 3+ (for cores and SRAM ports)  
473 pins  
Packages  
MAPBGA  
257 pins  
473 pins  
Temperature Ambient  
NOTES:  
See the TA recommended operating condition in the device data sheet  
1
Sphere of Replication.  
2
3
4
Does not include Test or Shadow Flash memory space.  
Available only on 473-pin package.  
DDR available only on 473 package. Other modules available as follows:  
EBI or DDR on 473 package.  
EBI + PDI on 473 package.  
DDR + PDI on 473 package  
PDI only on 257 package.  
1.3  
Block diagram  
Figure 1 shows a top-level block diagram of the PXS30 device.  
PXS30 Microcontroller Data Sheet, Rev. 1  
4
Preliminary—Subject to Change Without Notice  
Freescale Semiconductor  

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