Datasheet > SPQ7R4N40W

SPQ7R4N40W

更新时间： 2024-11-13 17:15:51

品牌	Logo	应用领域
中科君芯 - CAS-JUNSHINE		/
页数	文件大小	规格书
3页	546K
描述
LV-SGT

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中文翻译

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数据手册

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SPQ7R4N40W 数据手册

SPQ7R4N40W

SYMBOL

40V, 68A ⁽¹⁾N-Channel MOSFET

● Proprietary Trench Gate Device Design and Processes

● High Reliability Capability

Drain

● Sampled CP Probing and Inking

Gate

Source

℃

Electrical Characteristics in C/P Test (T_Jat 25 )

Symbol

V_(BR)DSS

R_DS(ON)

V_{GS (th)}

I_DSS

Parameter

Min. Typ. Max. Unit

Test Condition

Drain-Source Breakdown Voltage

Static Drain-Source On-Resistance

Gate Threshold Voltage

—

4.7

7.4

—

7.4

9.6

2.5

V_GS=0V, I_D=250µA

(2)

mΩ

V_GS=10V, I_D=1A

V_GS=4.5V, I_D=1A

V_DS=V_GS, I_D=250µA

V_DS=32V, V_GS=0V

V_DS=0V, V_GS=±20V

Drain-to-Source Leakage Current

Gate-Body Leakage Current

—

I_GSS

—

±100

T_J, T_STG

Operating and Storage Temperature

-55℃ to 150℃ Max.

Mechanical Data

Die Drawing

980 µ

Chip Size

m X 1542 m

Gate Pad Size

Source Pad Size

Scribe Line Width

Wafer Thickness

Wafer Diameter

Gross Die

160 m X 160 m

897 m X 1458 m

60 m

150 m

200 mm

17362 EA

Source Metallization

Drain Metallization

Passivation

Al-Cu (4 m typical)

Ti-Ni-Ag

N/A

Recommended Storage

Environment

Store in original container, in dry nitrogen, 6

months at ambient temperature of 23°C ± 3°C

(1) This characteristic assumes the die is assembled in SOP-8 package. Actual performance may degrade when

assembled.

(2) Pulse Width tp = < 1 mS, Duty Cycle < 2%.

Address: Floor 5, C1 Building, No. 200, Linghu Blvd., Wuxi, Jiangshu, China

Version: Preliminary Rev 0

1 ̶

12 3

中文翻译

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