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SNJ54LS224AFK PDF预览

SNJ54LS224AFK

更新时间： 2024-11-19 11:58:39
品牌 Logo 应用领域
德州仪器 - TI 存储内存集成电路输出元件先进先出芯片
页数 文件大小 规格书
13页 355K
描述
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS

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SNJ54LS224AFK 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QLCC
包装说明：CERAMIC, LCC-20针数：20
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.91
Is Samacsys：N最长访问时间：80 ns
JESD-30 代码：S-CQCC-N20长度：8.89 mm
内存密度：64 bit内存集成电路类型：OTHER FIFO
内存宽度：4功能数量：1
端子数量：20字数：16 words
字数代码：16工作模式：SYNCHRONOUS
最高工作温度：125 °C最低工作温度：-55 °C
组织：16X4可输出：YES
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装等效代码：LCC(UNSPEC)封装形状：SQUARE
封装形式：CHIP CARRIER并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified筛选级别：MIL-PRF-38535
座面最大高度：2.03 mm子类别：FIFOs
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：MILITARY
端子形式：NO LEAD端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：8.89 mmBase Number Matches：1

SNJ54LS224AFK 数据手册

 浏览型号SNJ54LS224AFK的Datasheet PDF文件第2页浏览型号SNJ54LS224AFK的Datasheet PDF文件第3页浏览型号SNJ54LS224AFK的Datasheet PDF文件第4页浏览型号SNJ54LS224AFK的Datasheet PDF文件第5页浏览型号SNJ54LS224AFK的Datasheet PDF文件第6页浏览型号SNJ54LS224AFK的Datasheet PDF文件第7页 
SN54LS224A, SN74LS224A  
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES  
WITH 3-STATE OUTPUTS  
SDLS023E – JANUARY 1991 – REVISED APRIL 2003  
SN54LS224A . . . J PACKAGE  
SN74LS224A . . . N PACKAGE  
(TOP VIEW)  
Independent Synchronous Inputs and  
Outputs  
16 Words by 4 Bits Each  
3-State Outputs Drive Bus Lines Directly  
Data Rates up to 10 MHz  
Fall-Through Time 50 ns Typical  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
OE  
IR  
LDCK  
D0  
D1  
D2  
D3  
GND  
CC  
UNCK  
OR  
Q0  
Q1  
Q2  
Q3  
CLR  
Data Terminals Arranged for Printed Circuit  
Board Layout  
Expandable, Using External Gating  
Packaged in Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs, and Ceramic Chip  
Carriers (FK)  
SN54LS224A . . . FK PACKAGE  
(TOP VIEW)  
description  
The SN54LS224A and SN74LS224A 64-bit,  
low-power Schottky memories are organized as  
16 words by 4 bits each. They can be expanded  
in multiples of 15m + 1 words or 4n bits, or both  
(where n is the number of packages in the vertical  
array and m is the number of packages in the  
horizontal array); however, some external gating  
is required. For longer words, the input-ready (IR)  
signals of the first-rank packages and  
output-ready (OR) signals of the last-rank  
packages must be ANDed for proper  
synchronization.  
3
9
2
1
20 19  
18  
LDCK  
D0  
OR  
Q0  
NC  
Q1  
Q2  
4
5
6
7
8
17  
16  
15  
14  
NC  
D1  
D2  
10 11 12 13  
NC – No internal connection  
A first-in, first-out (FIFO) memory is a storage  
device that allows data to be written to and read  
from its array at independent data rates. These  
FIFOs are designed to process data at rates up to  
10 MHz in a bit-parallel format, word by word.  
The load clock (LDCK) normally is held low, and data is written into memory on the high-to-low transition of  
LDCK. The unload clock (UNCK) normally is held high, and data is read out on the low-to-high transition of  
UNCK. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked  
out. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory  
is empty, UNCK signals have no effect.  
Status of the FIFO memory is monitored by the IR and OR flags that indicate not-full and not-empty conditions.  
IR is high only when the memory is not full and LDCK is low. OR is high only when the memory is not empty  
and UNCK is high.  
A low level on the clear (CLR) input resets the internal stack-control pointers and also sets IR high and OR low  
to indicate that old data remaining at the data outputs is invalid. Data outputs are noninverting, with respect to  
the data inputs, and are at high impedance when the output-enable (OE) input is low. OE does not affect the  
IR and OR outputs.  
The SN74LS224A is characterized for operation from 0°C to 70°C. The SN54LS224A is characterized over the  
full military temperature range of –55°C to 125°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
unless otherwise noted. On all other products, production  
testing of all parameters.  
processing does not necessarily include testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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