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SNJ54HCT125J PDF预览

SNJ54HCT125J

更新时间： 2024-11-02 14:27:03
品牌 Logo 应用领域
德州仪器 - TI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
7页 130K
描述
HCT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, CDIP14, CERAMIC, DIP-14

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SNJ54HCT125J 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：CERAMIC, DIP-14针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.5Is Samacsys：N
控制类型：ENABLE LOW系列：HCT
JESD-30 代码：R-GDIP-T14长度：19.56 mm
负载电容（CL）：150 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.006 A位数：1
功能数量：4端口数量：2
端子数量：14最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP14,.3
封装形状：RECTANGULAR封装形式：IN-LINE
包装方法：TUBE电源：5 V
Prop。Delay @ Nom-Sup：39 ns传播延迟（tpd）：58 ns
认证状态：Not Qualified筛选级别：MIL-PRF-38535
座面最大高度：5.08 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

SNJ54HCT125J 数据手册

 浏览型号SNJ54HCT125J的Datasheet PDF文件第2页浏览型号SNJ54HCT125J的Datasheet PDF文件第3页浏览型号SNJ54HCT125J的Datasheet PDF文件第4页浏览型号SNJ54HCT125J的Datasheet PDF文件第5页浏览型号SNJ54HCT125J的Datasheet PDF文件第6页浏览型号SNJ54HCT125J的Datasheet PDF文件第7页 
SN54HCT125, SN74HCT125  
QUADRUPLE BUS BUFFER GATES  
WITH 3-STATE OUTPUTS  
SCLS069D – NOVEMBER 1988 – REVISED MARCH 2003  
Operating Voltage Range of 4.5 V to 5.5 V  
±6-mA Output Drive at 5 V  
High-Current Outputs Drive Up To 15  
LSTTL Loads  
Low Input Current of 1 µA Max  
Inputs Are TTL-Voltage Compatible  
Low Power Consumption, 80-µA Max I  
CC  
High-Current 3-State Outputs Drive Bus  
Lines or Buffer Memory Address Registers  
Typical t = 12 ns  
pd  
SN54HCT125 . . . FK PACKAGE  
(TOP VIEW)  
SN54HCT125 . . . J OR W PACKAGE  
SN74HCT125 . . . D OR N PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
1Y  
2OE  
2A  
2Y  
V
CC  
4OE  
4A  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
4
5
6
7
8
17  
16  
4Y  
3OE  
3A  
2OE  
NC  
15 NC  
14  
9 10 11 12 13  
3OE  
2A  
8
GND  
3Y  
NC – No internal connection  
description/ordering information  
These bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the  
associated output-enable (OE) input is high.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
SOIC – D  
Tube  
SN74HCT125N  
SN74HCT125D  
SN74HCT125DR  
SNJ54HCT125J  
SNJ54HCT125W  
SNJ54HCT125FK  
SN74HCT125N  
–40°C to 85°C  
–55°C to 125°C  
Tube  
HCT125  
Tape and reel  
Tube  
CDIP – J  
CFP – W  
LCCC – FK  
SNJ54HCT125J  
SNJ54HCT125W  
SNJ54HCT125FK  
Tube  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
H
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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