5秒后页面跳转
捷配首页

Datasheet > SNJ54HC563WR
SNJ54HC563WR PDF预览

SNJ54HC563WR

更新时间： 2024-11-26 20:07:03
品牌 Logo 应用领域
德州仪器 - TI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
13页 630K
描述
HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CDFP20, CERAMIC, DFP-20

阅读下载

中文翻译

获取价格

SNJ54HC563WR 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：20
Reach Compliance Code：unknown风险等级：5.73
其他特性：BROADSIDE VERSION OF 533系列：HC/UH
JESD-30 代码：R-GDFP-F20长度：13.09 mm
负载电容（CL）：150 pF逻辑集成电路类型：BUS DRIVER
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
传播延迟（tpd）：285 ns认证状态：Not Qualified
筛选级别：MIL-PRF-38535座面最大高度：2.45 mm
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL宽度：6.92 mm
Base Number Matches：1

SNJ54HC563WR 数据手册

 浏览型号SNJ54HC563WR的Datasheet PDF文件第2页浏览型号SNJ54HC563WR的Datasheet PDF文件第3页浏览型号SNJ54HC563WR的Datasheet PDF文件第4页浏览型号SNJ54HC563WR的Datasheet PDF文件第5页浏览型号SNJ54HC563WR的Datasheet PDF文件第6页浏览型号SNJ54HC563WR的Datasheet PDF文件第7页 
SN54HC563, SN74HC563  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCLS145C – DECEMBER 1982 – REVISED MARCH 2003  
Wide Operating Voltage Range of 2 V to 6 V  
Typical t = 21 ns  
pd  
High-Current 3-State Outputs Drive Bus  
Lines Directly or Up To 15 LSTTL Loads  
±6-mA Output Drive at 5 V  
Low Input Current of 1 µA Max  
Bus-Structured Pinout  
Low Power Consumption, 80-µA Max I  
CC  
SN54HC563 . . . FK PACKAGE  
(TOP VIEW)  
SN54HC563 . . . J OR W PACKAGE  
SN74HC563 . . . DW OR N PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
3
2
1
20 19  
18  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
LE  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
GND  
description/ordering information  
These 8-bit transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
While the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When  
LE is taken low, the outputs are latched at the inverses of the levels set up at the D inputs.  
A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic  
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and increased high logic level provide the capability to drive bus lines  
without interface or pullup components.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74HC563N  
SN74HC563N  
–40°C to 85°C  
–55°C to 125°C  
Tube  
SN74HC563DW  
SN74HC563DWR  
SNJ54HC563J  
SNJ54HC563W  
SNJ54HC563FK  
SOIC – DW  
HC563  
Tape and reel  
Tube  
CDIP – J  
CFP – W  
LCCC – FK  
SNJ54HC563J  
SNJ54HC563W  
SNJ54HC563FK  
Tube  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

中文翻译

下载PDF

与SNJ54HC563WR相关器件

型号 品牌 获取价格 描述 数据表
SNJ54HC564FK-00 TI

获取价格

 		HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CQCC20
SNJ54HC573AFK TI

获取价格

 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SNJ54HC573AFKR TI

获取价格

 		HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20
SNJ54HC573AJ TI

获取价格

 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SNJ54HC573AW TI

获取价格

 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SNJ54HC573FK-00 TI

获取价格

 		HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20
SNJ54HC573J-00 TI

获取价格

 		HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20
SNJ54HC574FK TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54HC574FK-00 TI

获取价格

 		HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20
SNJ54HC574J TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

与SNJ54HC563WR相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证