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SNJ54HC590AWR PDF预览

SNJ54HC590AWR

更新时间： 2024-11-26 20:03:35
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
24页 950K
描述
HC/UH SERIES, ASYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, CDFP16, CERAMIC, DFP-16

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中文翻译

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SNJ54HC590AWR 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.46其他特性：RCO OUTPUT; REGISTERED OUTPUTS
计数方向：UP系列：HC/UH
JESD-30 代码：R-GDFP-F16长度：10.16 mm
负载电容（CL）：150 pF负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER工作模式：ASYNCHRONOUS
位数：8功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
传播延迟（tpd）：447 ns认证状态：Not Qualified
筛选级别：MIL-PRF-38535座面最大高度：2.03 mm
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：6.73 mm最小 fmax：16 MHz
Base Number Matches：1

SNJ54HC590AWR 数据手册

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SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003  
D
D
2-V to 6-V V  
Operation  
D
D
D
D
6-mA Output Drive at 5 V  
Low Input Current of 1 µA Max  
8-Bit Counter With Register  
Counter Has Direct Clear  
CC  
High-Current 3-State Parallel Register  
Outputs Can Drive Up To 15 LSTTL Loads  
D
Low Power Consumption, 80-µA Max I  
Typical t = 14 ns  
pd  
CC  
D
SN54HC590A . . . J OR W PACKAGE  
SN74HC590A . . . D, DW, OR N PACKAGE  
(TOP VIEW)  
SN54HC590A . . . FK PACKAGE  
(TOP VIEW)  
Q
Q
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
B
3
2
1
20 19  
18  
Q
C
D
A
Q
OE  
RCLK  
NC  
CCKEN  
CCLK  
4
5
6
7
8
D
Q
OE  
Q
17  
16  
15  
14  
E
Q
RCLK  
E
NC  
Q
12 CCKEN  
F
Q
F
11  
10  
9
Q
CCLK  
CCLR  
RCO  
G
Q
G
Q
9 10 11 12 13  
H
GND  
NC − No internal connection  
description/ordering information  
The ’HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register  
has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary  
counter features direct clear (CCLR) and count-enable (CCKEN) inputs. A ripple-carry output (RCO) is provided  
for cascading. Expansion is accomplished easily for two stages by connecting RCO of the first stage to CCKEN  
of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage  
to the counter clock (CCLK) input of the following stage.  
CCLK and the register clock (RCLK) inputs are positive-edge triggered. If both clocks are connected together,  
the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock  
enable.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Tube of 40  
Reel of 2000  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC590AN  
SN74HC590AD  
SN74HC590ADR  
SN74HC590ADT  
SN74HC590ADW  
SN74HC590ADWR  
SNJ54HC590AJ  
SNJ54HC590AW  
SNJ54HC590AFK  
SN74HC590AN  
HC590A  
−40°C to 85°C  
SOIC − DW  
HC590A  
CDIP − J  
CFP − W  
LCCC - FK  
SNJ54HC590AJ  
SNJ54HC590AW  
SNJ54HC590AFK  
−55°C to 125°C  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...24

中文翻译

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