5秒后页面跳转
SNJ54HC126W PDF预览

SNJ54HC126W

更新时间: 2024-11-20 05:16:55
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
19页 528K
描述
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

SNJ54HC126W 数据手册

 浏览型号SNJ54HC126W的Datasheet PDF文件第2页浏览型号SNJ54HC126W的Datasheet PDF文件第3页浏览型号SNJ54HC126W的Datasheet PDF文件第4页浏览型号SNJ54HC126W的Datasheet PDF文件第5页浏览型号SNJ54HC126W的Datasheet PDF文件第6页浏览型号SNJ54HC126W的Datasheet PDF文件第7页 
SN54HC126, SN74HC126  
QUADRUPLE BUS BUFFER GATES  
WITH 3-STATE OUTPUTS  
SCLS103E – MARCH 1984 – REVISED JULY 2003  
Wide Operating Voltage Range of 2 V to 6 V  
Typical t = 11 ns  
pd  
High-Current 3-State Outputs Interface  
Directly With System Bus or Can Drive Up  
To 15 LSTTL Loads  
6-mA Output Drive at 5 V  
Low Input Current of 1 µA Max  
Low Power Consumption, 80-µA Max I  
CC  
SN54HC126 . . . FK PACKAGE  
(TOP VIEW)  
SN54HC126 . . . J OR W PACKAGE  
SN74HC126 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
1OE  
1A  
V
CC  
13 4OE  
1
2
3
4
5
6
7
14  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
4
5
6
7
8
12  
11  
10  
9
1Y  
4A  
17  
16  
2OE  
2A  
4Y  
2OE  
NC  
3OE  
3A  
15 NC  
14  
9 10 11 12 13  
2Y  
3OE  
2A  
8
GND  
3Y  
NC – No internal connection  
description/ordering information  
These quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled  
when the associated output-enable (OE) input is low.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pullup  
resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
SOIC – D  
Tube of 25  
Tube of 50  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC126N  
SN74HC126N  
SN74HC126D  
SN74HC126DR  
SN74HC126DT  
SN74HC126NSR  
SN74HC126DBR  
SN74HC126PW  
SN74HC126PWR  
SN74HC126PWT  
SNJ54HC126J  
SNJ54HC126W  
SNJ54HC126FK  
HC126  
–40°C to 85°C  
SOP – NS  
HC126  
HC126  
SSOP – DB  
TSSOP – PW  
HC126  
CDIP – J  
CFP – W  
LCCC – FK  
SNJ54HC126J  
SNJ54HC126W  
SNJ54HC126FK  
–55°C to 125°C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

与SNJ54HC126W相关器件

型号 品牌 获取价格 描述 数据表
SNJ54HC126WR TI

获取价格

HC/UH SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, CDFP14, CERAMIC, DFP-14
SNJ54HC132FK TI

获取价格

QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
SNJ54HC132FK-00 TI

获取价格

HC/UH SERIES, QUAD 2-INPUT NAND GATE, CQCC20
SNJ54HC132J TI

获取价格

QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
SNJ54HC132J-00 TI

获取价格

HC/UH SERIES, QUAD 2-INPUT NAND GATE, CDIP14
SNJ54HC132W TI

获取价格

QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
SNJ54HC133FK-00 TI

获取价格

HC/UH SERIES, 13-INPUT NAND GATE, CQCC20
SNJ54HC133J TI

获取价格

HC/UH SERIES, 13-INPUT NAND GATE, CDIP16, 0.300 INCH, CERAMIC, DIP-16
SNJ54HC133J-00 TI

获取价格

HC/UH SERIES, 13-INPUT NAND GATE, CDIP16
SNJ54HC137FK-00 TI

获取价格

HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CQCC20