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SNJ54HC138J PDF预览

SNJ54HC138J

更新时间： 2024-11-19 22:41:03
品牌 Logo 应用领域
德州仪器 - TI 解码器解复用器
页数 文件大小 规格书
16页 537K
描述
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

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SNJ54HC138J 数据手册

 浏览型号SNJ54HC138J的Datasheet PDF文件第2页浏览型号SNJ54HC138J的Datasheet PDF文件第3页浏览型号SNJ54HC138J的Datasheet PDF文件第4页浏览型号SNJ54HC138J的Datasheet PDF文件第5页浏览型号SNJ54HC138J的Datasheet PDF文件第6页浏览型号SNJ54HC138J的Datasheet PDF文件第7页 
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SCLS107E − DECEMBER 1982 − REVISED SEPTEMBER 2003  
SN54HC138 . . . J OR W PACKAGE  
SN74HC138 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
Targeted Specifically for High-Speed  
Memory Decoders and Data-Transmission  
Systems  
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
A
B
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
Y0  
Y1  
Y2  
C
Low Power Consumption, 80-µA Max I  
CC  
G2A  
G2B  
G1  
Typical t = 15 ns  
pd  
4-mA Output Drive at 5 V  
12 Y3  
11  
10  
9
Y4  
Y5  
Y6  
Low Input Current of 1 µA Max  
Incorporate Three Enable Inputs to Simplify  
Cascading and/or Data Reception  
Y7  
GND  
SN54HC138 . . . FK PACKAGE  
(TOP VIEW)  
description/ordering information  
The ’HC138 devices are designed to be used in  
high-performance memory-decoding or data-  
routing applications requiring very short  
propagation delay times. In high-performance  
memory systems, these decoders can be used to  
minimize the effects of system decoding. When  
employed with high-speed memories utilizing a  
fast enable circuit, the delay times of these  
decoders and the enable time of the memory are  
usually less than the typical access time of the  
memory. This means that the effective system  
delay introduced by the decoders is negligible.  
3
2
1
20 19  
18  
Y1  
Y2  
NC  
C
G2A  
NC  
4
5
6
7
8
17  
16  
15 Y3  
14  
9 10 11 12 13  
G2B  
G1  
Y4  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC138N  
SN74HC138N  
SN74HC138D  
SN74HC138DR  
SN74HC138DT  
SN74HC138NSR  
SN74HC138DBR  
SN74HC138PW  
SN74HC138PWR  
SN74HC138PWT  
SNJ54HC138J  
HC138  
SOP − NS  
HC138  
HC138  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HC138  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC138J  
SNJ54HC138W  
SNJ54HC138FK  
SNJ54HC138W  
SNJ54HC138FK  
−55°C to 125°C  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
ꢐ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢔꢍ ꢌꢋ ꢖꢒ ꢯ ꢋꢇꢈꢂ ꢇꢂꢉ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

中文翻译

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SNJ54HC138J 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC237EE4 TI

完全替代

 High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches
5962-8406201VEA TI

完全替代

 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
8406201EA TI

完全替代

 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

与SNJ54HC138J相关器件

型号 品牌 获取价格 描述 数据表
SNJ54HC138J-00 TI

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 		HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDIP16
SNJ54HC138W TI

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 		3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SNJ54HC138WR TI

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 		HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDFP16, CERAMIC, DFP-16
SNJ54HC139FK TI

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 		DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SNJ54HC139FK-00 TI

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 		HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CQCC20
SNJ54HC139J TI

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 		DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SNJ54HC139J-00 TI

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 		HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDIP16
SNJ54HC139W TI

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 		DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SNJ54HC139WR TI

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 		HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDFP16, CERAMIC, DFP-16
SNJ54HC148FK TI

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 		8-LINE TO 3-LINE PRIORITY ENCODERS

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