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SNJ54HC112FK PDF预览

SNJ54HC112FK

更新时间: 2024-02-13 18:04:39
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
13页 430K
描述
DUAL J-NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

SNJ54HC112FK 技术参数

生命周期:Active零件包装代码:DFP
包装说明:DFP, FL16,.3针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.25系列:HC/UH
JESD-30 代码:R-GDFP-F16长度:10.3 mm
负载电容(CL):50 pF逻辑集成电路类型:J-K FLIP-FLOP
最大频率@ Nom-Sup:17000000 Hz最大I(ol):-0.004 A
位数:2功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装等效代码:FL16,.3封装形状:RECTANGULAR
封装形式:FLATPACK包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
最大电源电流(ICC):0.04 mAProp。Delay @ Nom-Sup:41 ns
传播延迟(tpd):185 ns认证状态:Not Qualified
施密特触发器:No筛选级别:MIL-PRF-38535
座面最大高度:2.03 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:6.73 mm
最小 fmax:20 MHzBase Number Matches:1

SNJ54HC112FK 数据手册

 浏览型号SNJ54HC112FK的Datasheet PDF文件第2页浏览型号SNJ54HC112FK的Datasheet PDF文件第3页浏览型号SNJ54HC112FK的Datasheet PDF文件第4页浏览型号SNJ54HC112FK的Datasheet PDF文件第5页浏览型号SNJ54HC112FK的Datasheet PDF文件第6页浏览型号SNJ54HC112FK的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢃꢄ ꢅꢆꢆꢇ  
ꢊꢋꢌ ꢍ ꢎ ꢏꢐ ꢁꢑ ꢒꢌꢓ ꢔꢕ ꢑꢏꢑꢊꢒ ꢑꢏ ꢓꢖꢔ ꢒ ꢒ ꢑꢖꢑ ꢊ ꢗ ꢍꢔ ꢘ ꢏꢗ ꢍꢙ ꢘꢀ  
ꢚ ꢔꢓ ꢄ ꢅꢍ ꢑꢌꢖ ꢌꢁꢊ ꢘ ꢖꢑ ꢀ ꢑꢓ  
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003  
SN54HC112 . . . J OR W PACKAGE  
SN74HC112 . . . D OR N PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
Low Power Consumption, 40-µA Max I  
CC  
1CLK  
1K  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
Typical t = 13 ns  
pd  
4-mA Output Drive at 5 V  
1CLR  
2CLR  
2CLK  
1J  
Low Input Current of 1 µA Max  
1PRE  
1Q  
12 2K  
description/ordering information  
11  
10  
9
1Q  
2J  
2Q  
2PRE  
2Q  
The ’HC112 devices contain two independent J-K  
negative-edge-triggered flip-flops. A low level at  
the preset (PRE) or clear (CLR) inputs sets or  
resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive  
(high), data at the J and K inputs meeting the  
setup time requirements are transferred to the  
outputs on the negative-going edge of the clock  
(CLK) pulse. Clock triggering occurs at a voltage  
level and is not directly related to the fall time of the  
CLK pulse. Following the hold-time interval, data  
at the J and K inputs may be changed without  
affecting the levels at the outputs. These versatile  
flip-flops perform as toggle flip-flops by tying J and  
K high.  
GND  
SN54HC112 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
2CLR  
2CLK  
NC  
1J  
1PRE  
NC  
4
5
6
7
8
17  
16  
15 2K  
14  
9 10 11 12 13  
1Q  
2J  
1Q  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC112N  
SN74HC112N  
SN74HC112D  
−40°C to 85°C  
SN74HC112DR  
SN74HC112DT  
SNJ54HC112J  
SNJ54HC112W  
SNJ54HC112FK  
HC112  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC112J  
−55°C to 125°C  
SNJ54HC112W  
SNJ54HC112FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢙ ꢜ ꢧ ꢟ ꢞꢪ ꢥꢤ ꢢꢣ ꢤꢞ ꢠꢧ ꢩꢛ ꢡꢜ ꢢ ꢢꢞ ꢱꢔ ꢍꢏ ꢘꢖ ꢗ ꢏꢲꢳꢂ ꢲꢂꢈ ꢡꢩꢩ ꢧꢡ ꢟ ꢡ ꢠꢦ ꢢꢦꢟ ꢣ ꢡ ꢟ ꢦ ꢢꢦ ꢣꢢꢦ ꢪ  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ  
ꢥ ꢜꢩ ꢦꢣꢣ ꢞ ꢢꢬꢦ ꢟ ꢮꢛ ꢣꢦ ꢜ ꢞꢢꢦ ꢪꢫ ꢙ ꢜ ꢡꢩ ꢩ ꢞ ꢢꢬꢦ ꢟ ꢧꢟ ꢞ ꢪꢥꢤ ꢢꢣ ꢈ ꢧꢟ ꢞ ꢪꢥꢤ ꢢꢛꢞ ꢜ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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