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SNJ54ALS563AFK PDF预览

SNJ54ALS563AFK

更新时间: 2024-11-20 15:52:27
品牌 Logo 应用领域
德州仪器 - TI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
4页 54K
描述
ALS SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CQCC20, CERAMIC, QCC-20

SNJ54ALS563AFK 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:CERAMIC, QCC-20
针数:20Reach Compliance Code:not_compliant
风险等级:5.87Is Samacsys:N
其他特性:BROADSIDE VERSION OF 533系列:ALS
JESD-30 代码:S-CQCC-N20长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:INVERTED
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC20,.35SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):26 mA
传播延迟(tpd):14 ns认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B座面最大高度:2.03 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8.89 mm
Base Number Matches:1

SNJ54ALS563AFK 数据手册

 浏览型号SNJ54ALS563AFK的Datasheet PDF文件第2页浏览型号SNJ54ALS563AFK的Datasheet PDF文件第3页浏览型号SNJ54ALS563AFK的Datasheet PDF文件第4页 
SN54ALS563A, SN74ALS563B  
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS  
SDAS163 – D2661, DECEMBER 1982 – REVISED JANUARY 1989  
SN54ALS563A . . . J PACKAGE  
SN74ALS563B . . . DW OR N PACKAGE  
3-State Buffer-Type Outputs Drive Bus-Lines  
Directly  
(TOP VIEW)  
Bus Structured Pinout  
Package Options include Plastic Small Outline  
Package, Ceramic Chip Carriers and Standard  
Plastic and Ceramic DIPs  
OC  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
C
Dependable Texas Instruments Quality and  
Reliability  
description  
These 8-bit latches feature three-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
GND  
SN54ALS563A . . . FK PACKAGE  
(TOP VIEW)  
The eight latches are transparent D-type latches.  
While the enable (C) is high the Q outputs will  
follow the complements of data (D) inputs. When  
the enable is taken low the output will be latched  
at the inverses of the levels that were set up at the  
D inputs.  
3
2
1
20 19  
18  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
A buffered output-control input can be used to  
place the eight outputs in either a normal logic  
9 10 11 12 13  
state (high or low logic levels) or  
a
high-impedance state. In the high-impedance  
state the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased high-logic level provide the capability to  
drive the bus lines in a bus-organized system  
without need for interface or pull-up components.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
The output control (OC) does not affect the  
internal operation of the latches. Old data can be  
retained or new data can be entered while the  
outputs are in the high-impedance state.  
ENABLE  
C
D
OC  
L
H
H
L
H
L
L
H
X
X
H
L
Q
0
The SN54ALS563A is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The SN74ALS563B is characterized for  
operation from 0°C to 70°C.  
H
X
Z
Copyright 1989, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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