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SNJ54ALS22BFK PDF预览

SNJ54ALS22BFK

更新时间: 2024-11-05 20:47:47
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 逻辑集成电路触发器
页数 文件大小 规格书
3页 53K
描述
NAND Gate, ALS Series, 2-Func, 4-Input, TTL, CQCC20, CERAMIC, LCC-20

SNJ54ALS22BFK 技术参数

生命周期:Contact Manufacturer包装说明:CERAMIC, LCC-20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.71系列:ALS
JESD-30 代码:S-CQCC-N20长度:8.89 mm
逻辑集成电路类型:NAND GATE功能数量:2
输入次数:4端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:OPEN-COLLECTOR封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装形状:SQUARE
封装形式:CHIP CARRIER传播延迟(tpd):65 ns
座面最大高度:2.03 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
宽度:8.89 mmBase Number Matches:1

SNJ54ALS22BFK 数据手册

 浏览型号SNJ54ALS22BFK的Datasheet PDF文件第2页浏览型号SNJ54ALS22BFK的Datasheet PDF文件第3页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢀ ꢆꢆ ꢇ ꢈꢉ ꢀꢁꢊ ꢃꢄ ꢅꢀ ꢆ ꢆꢇ  
ꢋꢌꢄ ꢅꢉꢃ ꢍꢎ ꢁꢏꢌ ꢐꢉ ꢏꢑ ꢀꢎ ꢐ ꢎꢒꢓ ꢍꢁꢄꢁꢋ ꢉ ꢔ ꢄꢐꢓ ꢀ  
ꢕ ꢎꢐ ꢖꢉ ꢑꢏ ꢓꢁꢍꢗꢑ ꢅ ꢅ ꢓꢗꢐꢑ ꢘꢉꢑ ꢌꢐ ꢏꢌ ꢐꢀ  
SDAS005A − MARCH 1984 − REVISED MAY 1986  
Package Options Include Plastic Small  
Outline Packages, Ceramic Chip Carriers,  
and Standard Plastic and Ceramic 300-mil  
DIPs  
SN54ALS22B . . . J PACKAGE  
SN74ALS22B . . . D OR N PACKAGE  
(TOP VIEW)  
1A  
1B  
NC  
1C  
1D  
1Y  
V
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
CC  
Dependable Texas Instruments Quality and  
2D  
2C  
NC  
2B  
2A  
2Y  
Reliability  
description  
These devices contain two independent 4-input  
NAND gates. They perform the Boolean functions  
Y = ABCD or Y = A+B+C+D in positive logic.  
The open-collector outputs require pullup  
resistors to perform correctly. They may be  
connected to other open-collector outputs to  
implement active-low wired-OR or active-high  
wired-AND functions. Open-collector devices are  
GND  
8
SN54ALS22B . . . FK PACKAGE  
(TOP VIEW)  
often used to generate higher V  
levels.  
OH  
3
2
1
20 19  
18  
The SN54ALS22B is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The SN74ALS22B is characterized for  
operation from 0°C to 70°C.  
2C  
NC  
NC  
NC  
2B  
NC  
NC  
1C  
NC  
1D  
4
5
6
7
8
17  
16  
15  
14  
FUNCTION TABLE  
(each gate)  
9 10 11 12 13  
INPUTS  
OUTPUT  
A
H
L
B
C
H
X
X
L
D
H
X
X
X
L
Y
L
NCNo internal connection  
H
X
L
H
H
H
H
X
X
X
logic diagram (positive logic)  
X
X
X
1A  
1B  
1C  
logic symbol  
1Y  
1
&
1D  
1A  
2
6
1B  
1Y  
2Y  
2A  
4
1C  
2B  
2C  
5
2Y  
1D  
9
2A  
2D  
8
10  
2B  
12  
2C  
13  
2D  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for D, J, and N packages.  
Copyright 1986, Texas Instruments Incorporated  
5BASIC  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  

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