SN75LVDS388DBTR

更新时间： 2024-11-20 09:12:03

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
14页	204K
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HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

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SN75LVDS388DBTR 数据手册

SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001

Eight Line Receivers Meet or Exceed the

Requirements of ANSI TIA/EIA-644

Standard

NOT RECOMMENDED FOR NEW DESIGNS

For Replacement Use ’LVDx388A

Integrated 110-Ω Line Termination

Resistors on LVDT Products

’LVDS388, ’LVDT388

DBT PACKAGE

(TOP VIEW)

†

Designed for Signaling Rates Up To

630 Mbps

A1A

A1B

A2A

A2B

B1A

B1B

B2A

B2B

C1A

C1B

C2A

C2B

D1A

D1B

D2A

D2B

GND

SN65 Version’s Bus-Terminal ESD Exceeds

15 kV

ENA

A1Y

A2Y

ENB

B1Y

B2Y

GND

Operates From a Single 3.3-V Supply

Propagation Delay Time of 2.6 ns (Typ)

Output Skew 100 ps (Typ)

Part-To-Part Skew Is Less Than 1 ns

LVTTL Levels Are 5-V Tolerant

Open-Circuit Fail Safe

Flow-Through Pin Out

GND

C1Y

C2Y

ENC

D1Y

D2Y

END

Packaged in Thin Shrink Small-Outline

Package With 20-mil Terminal Pitch

description

The ‘LVDS388 and ‘LVDT388 (T designates

integrated termination) are eight differential line

receivers that implement the electrical character-

istics of low-voltage differential signaling (LVDS).

Thissignalingtechniquelowerstheoutputvoltage

levels of 5-V differential standard levels (such as

EIA/TIA-422B) to reduce the power, increase the

switching speeds, and allow operation with a 3-V

supply rail. Any of the eight differential receivers

will provide a valid logical output state with a

+100-mV differential input voltage within the input

common-mode voltage range. The input

common-mode voltage range allows 1 V of

ground potential difference between two LVDS

nodes. Additionally, the high-speed switching of

LVDS signals always require the use of a line

impedance matching resistor at the receiving end

of the cable or transmission media. The LVDT

product eliminates this external resistor by

integrating it with the receiver.

GND

logic diagram (positive logic)

’LVDx388

’LVDT388 ONLY

(1/4 of ’LVDx388 shown)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...14

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与SN75LVDS388DBTR相关器件

型号	品牌	获取价格	描述	数据表
SN75LVDS388DBTRG4	TI	获取价格	OCTAL LINE RECEIVER, PDSO38, 0.50 MM PITCH, GREEN, PLASTIC, TSSOP-38
SN75LVDS389	TI	获取价格	HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SN75LVDS389DBT	TI	获取价格	HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SN75LVDS389DBTG4	TI	获取价格	HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SN75LVDS389DBTR	TI	获取价格	HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SN75LVDS389DBTRG4	TI	获取价格	HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SN75LVDS390	TI	获取价格	HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SN75LVDS390D	TI	获取价格	HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SN75LVDS390DG4	TI	获取价格	HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SN75LVDS390DR	TI	获取价格	HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

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