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SN75LVDS391PW PDF预览

SN75LVDS391PW

更新时间： 2024-11-19 22:53:31
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
18页 275K
描述
HIGH-SPEED DIFFERENTIAL LINE DRIVERS

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中文翻译

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SN75LVDS391PW 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP-16针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.21Is Samacsys：N
差分输出：YES驱动器位数：4
高电平输入电流最大值：0.00002 A输入特性：STANDARD
接口集成电路类型：LINE DRIVER接口标准：EIA-644; TIA-644
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：5 mm湿度敏感等级：1
功能数量：4端子数量：16
最高工作温度：70 °C最低工作温度：
最小输出摆幅：0.247 V输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大接收延迟：
座面最大高度：1.2 mm子类别：Line Driver or Receivers
最大压摆率：26 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
电源电压1-最大：3.6 V电源电压1-分钟：3 V
电源电压1-Nom：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED最大传输延迟：2.9 ns
宽度：4.4 mmBase Number Matches：1

SN75LVDS391PW 数据手册

 浏览型号SN75LVDS391PW的Datasheet PDF文件第2页浏览型号SN75LVDS391PW的Datasheet PDF文件第3页浏览型号SN75LVDS391PW的Datasheet PDF文件第4页浏览型号SN75LVDS391PW的Datasheet PDF文件第5页浏览型号SN75LVDS391PW的Datasheet PDF文件第6页浏览型号SN75LVDS391PW的Datasheet PDF文件第7页 
SN65LVDS387, SN75LVDS387, SN65LVDS389  
SN75LVDS389, SN65LVDS391, SN75LVDS391  
HIGH-SPEED DIFFERENTIAL LINE DRIVERS  
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001  
’LVDS389  
DBT PACKAGE  
(TOP VIEW)  
’LVDS387  
DGG PACKAGE  
(TOP VIEW)  
Four (’391), Eight (’389) or Sixteen (’387)  
Line Drivers Meet or Exceed the  
Requirements of ANSI EIA/TIA-644  
Standard  
GND  
A1Y  
A1Z  
A2Y  
A2Z  
A3Y  
A3Z  
A4Y  
A4Z  
B1Y  
B1Z  
B2Y  
B2Z  
B3Y  
B3Z  
B4Y  
B4Z  
C1Y  
C1Z  
C2Y  
C2Z  
C3Y  
C3Z  
C4Y  
C4Z  
D1Y  
D1Z  
D2Y  
D2Z  
D3Y  
D3Z  
D4Y  
D4Z  
1
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
GND  
A1Y  
1
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
†
Designed for Signaling Rates up to  
V
2
V
A1Z  
A2Y  
A2Z  
A3Y  
A3Z  
A4Y  
A4Z  
NC  
CC  
2
CC  
630 Mbps With Very Low Radiation (EMI)  
V
3
GND  
ENA  
A1A  
A2A  
A3A  
A4A  
GND  
CC  
3
GND  
ENA  
A1A  
A2A  
A3A  
A4A  
ENB  
B1A  
B2A  
B3A  
B4A  
GND  
Low-Voltage Differential Signaling With  
Typical Output Voltage of 350 mV and a  
100-Ω Load  
4
4
5
5
6
6
7
Propagation Delay Times Less Than 2.9 ns  
Output Skew Is Less Than 150 ps  
7
8
8
9
9
Part-to-Part Skew Is Less Than 1.5 ns  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
V
NC  
10  
11  
12  
13  
14  
15  
16  
CC  
35-mW Total Power Dissipation in Each  
Driver Operating at 200 MHz  
GND  
B1A  
B2A  
B3A  
B4A  
ENB  
NC  
B1Y  
B1Z  
B2Y  
B2Z  
B3Y  
B3Z  
B4Y  
B4Z  
Driver Is High Impedance When Disabled or  
With V  
< 1.5 V  
CC  
SN65’ Version Bus-Pin ESD Protection  
Exceeds 15 kV  
V
CC  
V
CC  
GND 17  
18  
GND 19  
Packaged in Thin Shrink Small-Outline  
Package With 20-mil Terminal Pitch  
GND  
C1A  
C2A  
C3A  
C4A  
ENC  
D1A  
D2A  
D3A  
D4A  
END  
GND  
V
CC  
Low-Voltage TTL (LVTTL) Logic Inputs Are  
5-V Tolerant  
’LVDS391  
D OR PW PACKAGE  
(TOP VIEW)  
description  
This family of four, eight, and sixteen differential  
line drivers implements the electrical characteris-  
tics of low-voltage differential signaling (LVDS).  
Thissignalingtechniquelowerstheoutputvoltage  
levels of 5-V differential standard levels (such as  
EIA/TIA-422B) to reduce the power, increase the  
switching speeds, and allow operation with a  
3.3-V supply rail. Any of the sixteen current-mode  
drivers will deliver a minimum differential output  
voltage magnitude of 247 mV into a 100-Ω load  
when enabled.  
EN1,2  
1Y  
1Z  
2Y  
2Z  
3Y  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
1A  
2A  
V
CC  
GND  
3A  
V
11 3Z  
10 4Y  
CC  
V
4A  
CC  
GND  
EN3,4  
9
4Z  
Theintendedapplicationofthisdeviceandsignalingtechniqueisforpoint-to-pointandmultidropbasebanddata  
transmission over controlled impedance media of approximately 100 Ω. The transmission media can be  
printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same  
substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of  
clock and data for synchronous parallel data transfers. When used with the companion 16- or 8-channel  
receivers, the SN65LVDS386 or SN65LVDS388, over 300 million data transfers per second in single-edge  
clocked systems are possible with very little power. (Note: The ultimate rate and distance of data transfer is  
dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other  
system characteristics.)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...18

中文翻译

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SN75LVDS391PW 替代型号

型号 品牌 替代类型 描述 数据表
SN75LVDS391PWR TI

完全替代

 HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SN75LVDS391PWRG4 TI

类似代替

 HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SN75LVDS391PWG4 TI

类似代替

 HIGH-SPEED DIFFERENTIAL LINE DRIVERS

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 		FlatLink&#153; Receiver 56-TSSOP 0 to 70

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