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SN75ALS164_14 PDF预览

SN75ALS164_14

更新时间: 2024-11-21 02:58:43
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德州仪器 - TI /
页数 文件大小 规格书
13页 200K
描述
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER

SN75ALS164_14 数据手册

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SN75ALS164  
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER  
SLLS022C – JUNE 1986 – REVISED MAY 1998  
DW PACKAGE  
8-Channel Bidirectional Transceiver  
(TOP VIEW)  
Designed to Implement Control Bus  
Interface  
SC  
TE  
V
CC  
1
24  
23  
Designed for Multiple-Controller Systems  
ATN + EOI  
2
High-Speed Advanced Low-Power Schottky  
Circuitry  
REN  
IFC  
3
22 REN  
21 IFC  
4
Low-Power Dissipation . . . 46 mW Max Per  
Channel  
5
20  
19  
18  
17  
16  
15  
14  
13  
NDAC  
NRFD  
DAV  
EOI  
ATN  
SRQ  
NC  
NDAC  
NRFD  
DAV  
EOI  
ATN  
SRQ  
NC  
GPIB  
I/O Ports  
6
Terminal  
I/O Ports  
7
Fast Propagation Times . . . 20 ns Max  
High-Impedance pnp Inputs  
8
9
Receiver Hysteresis . . . 650 mV Typ  
10  
11  
12  
Bus-Terminating Resistors Provided on  
Driver Outputs  
GND  
DC  
No Loading of Bus When Device Is  
Powered Down (V  
= 0)  
CC  
NC – No internal connection  
Power-Up/Power-Down Protection  
(Glitch Free)  
NOT RECOMMENDED FOR NEW DESIGNS  
description  
The SN75ALS164 eight-channel general-purpose interface bus transceiver is a monolithic, high-speed,  
advanced low-power Schottky device designed to meet the requirements of IEEE Standard 488-1978. Each  
transceiver is designed to provide the bus-management and data-transfer signals between operating units of  
a multiple-controller instrumentation system. When combined with the SN75ALS160 octal bus transceiver, the  
SN75ALS164 provides the complete 16-wire interface for the IEEE 488 bus.  
The SN75ALS164 features eight driver-receiver pairs connected in a front-to-back configuration to form  
input/output (I/O) ports at both the bus and terminal sides. All outputs are disabled (at the high-impedance state)  
during V  
power-up and power-down transitions for glitch-free operation. The direction of data flow through  
CC  
these driver-receiver pairs is determined by the DC, TE, and SC enable signals. The SN75ALS164 is identical  
to the SN75ALS162 with the addition of an OR gate to help simplify board layouts in several popular  
applications. The ATN and EOI signals are ORed to provide the ATN + EOI output, which is a standard  
totem-pole output.  
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high  
impedance to the bus when supply voltage V  
is 0. The drivers are designed to handle loads up to 48 mA of  
CC  
sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV  
minimum for increased noise immunity. All receivers have 3-state outputs that present a high impedance to the  
terminal when disabled.  
The SN75ALS164 is characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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