5秒后页面跳转
捷配首页

Datasheet > SN74LVTH16373-EP_16
SN74LVTH16373-EP_16 PDF预览

SN74LVTH16373-EP_16

更新时间： 2024-01-27 15:29:08
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
12页 462K
描述
SN74LVTH16373-EP 3.3-V ABT 16-Bit Transparent D-Type Latch With Tri-State Outputs

阅读下载

中文翻译

获取价格

SN74LVTH16373-EP_16 数据手册

 浏览型号SN74LVTH16373-EP_16的Datasheet PDF文件第2页浏览型号SN74LVTH16373-EP_16的Datasheet PDF文件第3页浏览型号SN74LVTH16373-EP_16的Datasheet PDF文件第4页浏览型号SN74LVTH16373-EP_16的Datasheet PDF文件第5页浏览型号SN74LVTH16373-EP_16的Datasheet PDF文件第6页浏览型号SN74LVTH16373-EP_16的Datasheet PDF文件第7页 
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢊ
ꢂ
ꢊ
ꢋ
ꢌ
ꢍ
ꢊ
ꢎ
ꢊ
ꢋ
ꢅ
ꢏ
ꢐ
ꢆ
ꢈ
ꢉ
ꢋ
ꢐ
ꢑ
ꢆ
ꢆ
ꢒ
ꢏ
ꢁ
ꢀ
ꢍ
ꢏ
ꢒ
ꢌ
ꢁ
ꢆ
ꢖ ꢑꢆ ꢇ ꢊ ꢋꢀꢆꢏꢆ ꢌ ꢗ ꢘꢆ ꢍꢘ ꢆꢀ  
ꢓ
ꢋ
ꢆ
ꢔ
ꢍ
ꢌ
ꢄ
ꢏ
ꢆ
ꢕ
ꢇ
SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004  
D
D
D
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
D
Flow-Through Architecture Optimizes PCB  
Layout  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Enhanced Product-Change Notification  
†
Qualification Pedigree  
Member of the Texas Instruments  
WidebusFamily  
DGG OR DL PACKAGE  
(TOP VIEW)  
D
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
2
3
4
D
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
5
6
3.3-V V  
)
CC  
7
V
V
CC  
CC  
D
D
D
D
Supports Unregulated Battery Operation  
Down to 2.7 V  
8
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
9
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
= 3.3 V, T = 25°C  
A
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
D
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
V
V
CC  
CC  
†
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
2D5  
2D6  
GND  
2D7  
2D8  
2LE  
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
description/ordering information  
The SN74LVTH16373 is a 16-bit transparent D-type latch with 3-state outputs designed for low-voltage (3.3-V)  
operation, but with the capability to provide a TTL interface to a 5-V system environment. This device is  
V
CC  
particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.  
This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the  
Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the  
D inputs.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
ꢍ
ꢍ
ꢒ
ꢗ
ꢨ
ꢓ
ꢣ
ꢘ
ꢕ
ꢡ
ꢆ
ꢢ
ꢑ
ꢜ
ꢗ
ꢚ
ꢁ
ꢛ
ꢓ
ꢏ
ꢆ
ꢏ
ꢙ
ꢚ
ꢤ
ꢛ
ꢜ
ꢢ
ꢝ
ꢞ
ꢟ
ꢟ
ꢠ
ꢠ
ꢙ
ꢙ
ꢜ
ꢜ
ꢚ
ꢚ
ꢙ
ꢡ
ꢡ
ꢥ
ꢢ
ꢣ
ꢝ
ꢝ
ꢤ
ꢤ
ꢚ
ꢠ
ꢟ
ꢞ
ꢡ
ꢡ
ꢜ
ꢛ
ꢥ
ꢆꢤ  
ꢣ
ꢦ
ꢡ
ꢧ
ꢙ
ꢢ
ꢟ
ꢡ
ꢠ
ꢙ
ꢠ
ꢜ
ꢝ
ꢚ
ꢣ
ꢨ
ꢟ
ꢚ
ꢠ
ꢠ
ꢤ
ꢡ
ꢎ
Copyright 2004, Texas Instruments Incorporated  
ꢝ
ꢜ
ꢢ
ꢠ
ꢜ
ꢝ
ꢞ
ꢠ
ꢜ
ꢡ
ꢥ
ꢙ
ꢛ
ꢙ
ꢢ
ꢤ
ꢝ
ꢠ
ꢩ
ꢠ
ꢤ
ꢝ
ꢜ
ꢛ
ꢪ
ꢟ
ꢑ
ꢚ
ꢞ
ꢤ
ꢡ
ꢠ
ꢟ
ꢚ
ꢨ
ꢟ
ꢝ
ꢨ
ꢫ
ꢟ
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢭ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢎ  
ꢝ
ꢝ
ꢟ
ꢚ
ꢠ
ꢬ
ꢎ
ꢍ
ꢝ
ꢜ
ꢨ
ꢣ
ꢢ
ꢠ
ꢙ
ꢜ
ꢚ
ꢥ
ꢝ
ꢜ
ꢢ
ꢤ
ꢡ
ꢡ
ꢙ
ꢚ
ꢭ
ꢨ
ꢜ
ꢤ
ꢡ
ꢚ
ꢜ
ꢠ
ꢚ
ꢤ
ꢢ
ꢤ
ꢡ
ꢡ
ꢟ
ꢝ
ꢙ
ꢧ
ꢬ
ꢙ
ꢚ
ꢢ
ꢧ
ꢣ
ꢨ
ꢤ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

下载PDF

与SN74LVTH16373-EP_16相关器件

型号 品牌 获取价格 描述 数据表
SN74LVTH16373GQLR TI

获取价格

 		3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74LVTH16373GRDR TI

获取价格

 		3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74LVTH16373ZQLR TI

获取价格

 		3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74LVTH16373ZRDR TI

获取价格

 		3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74LVTH16374 TI

获取价格

 		3.3V ABT 16 BIT EDGE - TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
SN74LVTH16374DGG TI

获取价格

 		3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LVTH16374DGGR TI

获取价格

 		3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LVTH16374DL TI

获取价格

 		3.3V ABT 16 BIT EDGE - TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
SN74LVTH16374DLG4 TI

获取价格

 		3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LVTH16374DLR TI

获取价格

 		3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

与SN74LVTH16373-EP_16相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证