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SN74LVTH16500 PDF预览

SN74LVTH16500

更新时间： 2024-11-19 23:09:43
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德州仪器 - TI 输出元件
页数 文件大小 规格书
9页 138K
描述
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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SN74LVTH16500 数据手册

 浏览型号SN74LVTH16500的Datasheet PDF文件第2页浏览型号SN74LVTH16500的Datasheet PDF文件第3页浏览型号SN74LVTH16500的Datasheet PDF文件第4页浏览型号SN74LVTH16500的Datasheet PDF文件第5页浏览型号SN74LVTH16500的Datasheet PDF文件第6页浏览型号SN74LVTH16500的Datasheet PDF文件第7页 
SN54LVTH16500, SN74LVTH16500  
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS701D – JULY 1997 – REVISED APRIL 1999  
SN54LVTH16500 . . . WD PACKAGE  
SN74LVTH16500 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
OEAB  
LEAB  
A1  
GND  
A2  
GND  
CLKAB  
B1  
GND  
B2  
1
2
3
4
5
6
7
8
9
56  
55  
54  
53  
52  
51  
50  
49  
48  
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
A3  
B3  
V
V
CC  
CC  
A4  
A5  
B4  
B5  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
)
CC  
A6 10  
47 B6  
Support Unregulated Battery Operation  
Down to 2.7 V  
GND  
A7  
GND  
B7  
11  
12  
46  
45  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
A8 13  
A9 14  
44 B8  
= 3.3 V, T = 25°C  
CC  
A
43 B9  
I
and Power-Up 3-State Support Hot  
off  
A10 15  
A11 16  
A12 17  
GND 18  
A13 19  
A14 20  
A15 21  
42 B10  
41 B11  
40 B12  
39 GND  
38 B13  
37 B14  
36 B15  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
V
22  
35  
V
Flow-Through Architecture Optimizes PCB  
Layout  
CC  
CC  
A16 23  
34 B16  
33 B17  
32 GND  
31 B18  
30 CLKBA  
29 GND  
A17 24  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
GND 25  
A18 26  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
OEBA 27  
LEBA 28  
Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
The ’LVTH16500 devices are 18-bit universal bus transceivers designed for low-voltage (3.3-V) V operation,  
CC  
but with the capability to provide a TTL interface to a 5-V system environment.  
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),  
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when  
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is  
low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. Output-enable OEAB is  
active high. When OEAB is high, the B-port outputs are active. When OEAB is low, the B-port outputs are in the  
high-impedance state.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and UBT are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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