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SN74LVTH16501 PDF预览

SN74LVTH16501

更新时间: 2024-11-19 23:09:43
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德州仪器 - TI 输出元件
页数 文件大小 规格书
12页 202K
描述
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SN74LVTH16501 数据手册

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SN54LVTH16501, SN74LVTH16501  
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS700E – JULY 1997 – REVISED NOVEMBER 2002  
SN54LVTH16501 . . . WD PACKAGE  
SN74LVTH16501 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
UBT Transceiver Combines D-Type  
Latches and D-Type Flip-Flops for  
Operation in Transparent, Latched, or  
Clocked Mode  
OEAB  
LEAB  
A1  
GND  
A2  
GND  
CLKAB  
B1  
GND  
B2  
1
2
3
4
5
6
7
8
9
56  
55  
54  
53  
52  
51  
50  
49  
48  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
A3  
B3  
V
V
CC  
CC  
A4  
A5  
B4  
B5  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
)
CC  
A6 10  
47 B6  
Support Unregulated Battery Operation  
Down to 2.7 V  
GND  
A7  
GND  
B7  
11  
12  
46  
45  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
A8 13  
A9 14  
44 B8  
= 3.3 V, T = 25°C  
A
43 B9  
I
and Power-Up 3-State Support Hot  
off  
A10 15  
A11 16  
A12 17  
GND 18  
A13 19  
A14 20  
A15 21  
42 B10  
41 B11  
40 B12  
39 GND  
38 B13  
37 B14  
36 B15  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
V
22  
35  
V
Flow-Through Architecture Optimizes PCB  
Layout  
CC  
CC  
A16 23  
34 B16  
33 B17  
32 GND  
31 B18  
30 CLKBA  
29 GND  
A17 24  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
GND 25  
A18 26  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
OEBA 27  
LEBA 28  
description/ordering information  
The ’LVTH16501 devices are 18-bit universal bus transceivers designed for low-voltage (3.3-V) V operation,  
CC  
but with the capability to provide a TTL interface to a 5-V system environment.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Tube  
SN74LVTH16501DL  
SN74LVTH16501DLR  
SN74LVTH16501DGGR  
SNJ54LVTH16501WD  
SSOP – DL  
LVTH16501  
–40°C to 85°C  
–55°C to 125°C  
Tape and reel  
Tape and reel  
Tube  
TSSOP – DGG  
CFP – WD  
LVTH16501  
SNJ54LVTH16501WD  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available  
at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and UBT are trademarks of Texas Instruments.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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