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SN74LVTH16500GQLR PDF预览

SN74LVTH16500GQLR

更新时间: 2024-11-20 05:29:31
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
16页 391K
描述
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SN74LVTH16500GQLR 数据手册

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ꢍ ꢎꢍ ꢏꢅ ꢐꢑꢆ ꢈ ꢒ ꢏꢑꢓ ꢆ ꢔꢁꢓ ꢅꢕ ꢖꢀꢐꢄ ꢑꢔꢀ ꢆ ꢖꢐꢁꢀ ꢗꢕ ꢓ ꢅꢕ ꢖ  
SCBS701F − JULY 1997 − REVISED SEPTEMBER 2003  
SN54LVTH16500 . . . WD PACKAGE  
SN74LVTH16500 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
D
D
Members of the Texas Instruments  
WidebusFamily  
UBT Transceivers Combine D-Type  
Latches and D-Type Flip-Flops for  
Operation in Transparent, Latched, or  
Clocked Mode  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEAB  
LEAB  
A1  
GND  
A2  
GND  
CLKAB  
B1  
GND  
B2  
2
3
D
D
D
D
D
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
4
)
5
CC  
6
A3  
B3  
Support Unregulated Battery Operation  
Down to 2.7 V  
7
V
V
CC  
CC  
8
A4  
A5  
A6  
GND  
A7  
B4  
B5  
B6  
GND  
B7  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
9
= 3.3 V, T = 25°C  
A
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
A8  
A9  
B8  
B9  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
D
D
D
D
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
Flow-Through Architecture Optimizes PCB  
Layout  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
V
V
CC  
CC  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
A16  
A17  
GND  
A18  
OEBA  
LEBA  
B16  
B17  
GND  
B18  
CLKBA  
GND  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
The ’LVTH16500 devices are 18-bit universal bus  
transceivers designed for low-voltage (3.3-V) V  
CC  
operation, but with the capability to provide a TTL  
interface to a 5-V system environment.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
T
A
PACKAGE  
TOP-SIDE MARKING  
Tube  
SN74LVTH16500DL  
SSOP − DL  
LVTH16500  
LVTH16500  
Tape and reel  
Tape and reel  
SN74LVTH16500DLR  
SN74LVTH16500DGGR  
SN74LVTH16500GQLR  
SN74LVTH16500ZQLR  
SNJ54LVTH16500WD  
TSSOP − DGG  
VFBGA − GQL  
−40°C to 85°C  
−55°C to 125°C  
Tape and reel  
Tube  
LL500  
VFBGA − ZQL (Pb-free)  
CFP − WD  
SNJ54LVTH16500WD  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and UBT are trademarks of Texas Instruments.  
Copyright 2003, Texas Instruments Incorporated  
ꢔ ꢁ ꢄꢕꢀꢀ ꢙ ꢆꢇ ꢕꢖꢘ ꢓꢀ ꢕ ꢁ ꢙꢆꢕꢛ ꢜꢝ ꢞꢟ ꢠꢡꢢ ꢣꢤꢥ ꢦꢜ ꢢꢡ ꢦꢜꢧ ꢞꢦꢟ ꢚꢖ ꢙ ꢛ ꢔ ꢗꢆ ꢓꢙ ꢁ  
ꢩꢤ  
ꢪꢧ ꢩ ꢧ ꢤ ꢥ ꢜ ꢥ ꢩ ꢟ ꢎ  
ꢧꢩ  
ꢟꢜ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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