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SN74LVCZ161284A PDF预览

SN74LVCZ161284A

更新时间: 2024-11-28 22:16:15
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德州仪器 - TI /
页数 文件大小 规格书
10页 161K
描述
19-BIT IEEE 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP

SN74LVCZ161284A 数据手册

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SN74LVCZ161284A  
19-BIT IEEE 1284 TRANSLATION TRANSCEIVER  
WITH ERROR-FREE POWER UP  
SCES358B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002  
DGG PACKAGE  
(TOP VIEW)  
Power-On Reset (POR) Prevents Printer  
Errors When Printer Is Turned On, But No  
Valid Signal Is at Pins A9–A13  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
HD  
A9  
DIR  
Y9  
Operates From 3 V to 3.6 V  
2
1.4-kPullup Resistors Integrated on All  
Open-Drain Outputs Eliminate the Need for  
Discrete Resistors  
3
A10  
A11  
A12  
A13  
Y10  
Y11  
Y12  
Y13  
4
5
Designed for the IEEE Std 1284-I (Level-1  
Type) and IEEE Std 1284-II (Level-2 Type)  
Electrical Specifications  
6
7
V
V
CABLE  
CC  
A1  
CC  
8
B1  
9
A2  
GND  
A3  
A4  
A5  
A6  
GND  
A7  
B2  
GND  
B3  
B4  
B5  
B6  
GND  
B7  
B8  
V
Flow-Through Architecture Optimizes PCB  
Layout  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
– 4000-V Human-Body Model (A114-A)  
– 350-V Machine Model (A115-A)  
A8  
V
CABLE  
CC  
CC  
– 1500-V Charged-Device Model (C101)  
PERI LOGIC IN  
PERI LOGIC OUT  
C14  
C15  
C16  
A14  
A15  
A16  
A17  
description/ordering information  
The SN74LVCZ161284A is designed for 3-V to  
3.6-V V  
operation. This device provides  
C17  
CC  
asynchronous two-way communication between  
data buses. The control-function implementation  
minimizes external timing requirements.  
HOST LOGIC OUT  
HOST LOGIC IN  
This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control  
input (DIR) is high, and in the B-to-A direction when DIR is low. This device also has five drivers that drive the  
cable side and four receivers. The SN74LVCZ161284A has one receiver dedicated to the HOST LOGIC line  
and a driver to drive the PERI LOGIC line.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
PACKAGE  
TSSOP – DGG  
A
0°C to 70°C  
Tape and reel SN74LVCZ161284AGR  
LVCZ161284A  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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