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SN74LVC1G86ADCK

更新时间： 2024-10-01 13:13:51
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德州仪器 - TI 输入元件
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SN74LVC1G86  
SINGLE 2-INPUT EXCLUSIVE-OR GATE  
www.ti.com  
SCES222N–APRIL 1999–REVISED FEBRUARY 2007  
FEATURES  
•
Available in the Texas Instruments  
NanoFree™ Package  
Operation  
•
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
•
•
•
•
•
Supports 5-V VCC Operation  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4 ns at 3.3 V  
ESD Protection Exceeds JESD 22  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
Ioff Supports Partial-Power-Down Mode  
1000-V Charged-Device Model (C101)  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
3
2
1
4
GND  
B
Y
VCC  
1
2
3
5
VCC  
A
B
1
2
3
5
A
VCC  
1
2
3
5
4
A
B
B
5
VCC  
A
4
GND  
Y
4
GND  
Y
GND  
Y
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.  
The SN74LVC1G86 performs the Boolean function Y = A B or Y = AB + AB in positive logic.  
A common application is as a true/complement element. If the input is low, the other input is reproduced in true  
form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
Reel of 3000  
SN74LVC1G86YZPR  
_ _ _CH_  
Reel of 3000  
Reel of 250  
Reel of 3000  
Reel of 250  
SN74LVC1G86DBVR  
SN74LVC1G86DBVT  
SN74LVC1G86DCKR  
SN74LVC1G86DCKT  
SOT (SOT-23) – DBV  
SOT (SC-70) – DCK  
C86_  
CH_  
–40°C to 85°C  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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