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SN74LVC1G32DPWR PDF预览

SN74LVC1G32DPWR

更新时间: 2024-11-25 11:07:59
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路
页数 文件大小 规格书
17页 443K
描述
单路 2 输入、1.65V 至 5.5V 或门 | DPW | 5 | -40 to 125

SN74LVC1G32DPWR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:HVSON,
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.56
系列:LVC/LCX/ZJESD-30 代码:S-PDSO-N4
JESD-609代码:e4长度:0.8 mm
逻辑集成电路类型:OR GATE最大I(ol):0.032 A
湿度敏感等级:1功能数量:1
输入次数:2端子数量:4
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HVSON
封装形状:SQUARE封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260传播延迟(tpd):9 ns
座面最大高度:0.4 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.48 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:0.8 mmBase Number Matches:1

SN74LVC1G32DPWR 数据手册

 浏览型号SN74LVC1G32DPWR的Datasheet PDF文件第2页浏览型号SN74LVC1G32DPWR的Datasheet PDF文件第3页浏览型号SN74LVC1G32DPWR的Datasheet PDF文件第4页浏览型号SN74LVC1G32DPWR的Datasheet PDF文件第5页浏览型号SN74LVC1G32DPWR的Datasheet PDF文件第6页浏览型号SN74LVC1G32DPWR的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊ  
ꢀꢋ ꢁꢈ ꢄ ꢌ ꢊ ꢍꢋꢁ ꢎꢏꢐ ꢎꢑ ꢀꢋ ꢐ ꢋꢅꢌ ꢍꢑ ꢒ ꢈ ꢓꢐꢌ  
SCES219N − APRIL 1999 − REVISED JUNE 2005  
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
D
D
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
D
D
D
D
D
Supports 5-V V  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
CC  
Inputs Accept Voltages to 5.5 V  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Max t of 3.6 ns at 3.3 V  
pd  
Low Power Consumption, 10-µA Max I  
CC  
24-mA Output Drive at 3.3 V  
− 1000-V Charged-Device Model (C101)  
YEA, YEP, YZA,  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
OR YZP PACKAGE  
(BOTTOM VIEW)  
3
2
1
4
5
Y
GND  
B
1
2
3
5
A
V
Y
A
B
V
1
2
3
5
CC  
CC  
1
2
3
5
A
B
V
Y
CC  
B
V
A
CC  
4
GND  
Y
4
GND  
4
GND  
See mechanical drawings for dimensions.  
description/ordering information  
This single 2-input positive-OR gate is designed for 1.65-V to 5.5-V V  
operation.  
CC  
The SN74LVC1G32 performs the Boolean function Y + A ) B or Y + A B in positive logic.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
ꢐꢠ  
Copyright 2005, Texas Instruments Incorporated  
ꢜ ꢠ ꢝ ꢜꢕ ꢖꢪ ꢘꢗ ꢛ ꢣꢣ ꢡꢛ ꢙ ꢛ ꢚ ꢠ ꢜ ꢠ ꢙ ꢝ ꢥ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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