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SN74LVC1G32-EP PDF预览

SN74LVC1G32-EP

更新时间： 2024-11-27 12:15:03
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德州仪器 - TI 输入元件
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描述
SINGLE 2-INPUT POSITIVE-OR GATE

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SN74LVC1G32-EP 数据手册

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SN74LVC1G32-EP  
SINGLE 2-INPUT POSITIVE-OR GATE  
www.ti.com  
SCES458D–DECEMBER 2003–REVISED JUNE 2007  
FEATURES  
•
Controlled Baseline  
•
•
•
Ioff Supports Partial Power Down Mode  
Operation  
–
One Assembly/Test Site, One Fabrication  
Site  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
•
Extended Temperature Performance of –55°C  
to 125°C  
ESD Protection Exceeds JESD 22  
Enhanced Diminishing Manufacturing Sources  
(DMS) Support  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
•
•
•
•
•
•
•
Enhanced Product-Change Notification  
1000-V Charged-Device Model (C101)  
(1)  
Qualification Pedigree  
DBV OR DCK PACKAGE  
(TOP VIEW)  
Supports 5-V VCC Operation  
Inputs Accept Voltages to 5.5 V  
Max tpd of 3.6 ns at 3.3 V  
1
2
3
5
4
A
B
V
Y
CC  
Low Power Consumption, 10 μA Max ICC  
±24-mA Output Drive at 3.3 V  
GND  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
DESCRIPTION/ORDERING INFORMATION  
This single 2-input positive-OR gate is designed for 1.65-V to 5.5-V VCC operation.  
Y + A ) B or Y + A • B  
The SN74LVC1G32 performs the Boolean function  
in positive logic.  
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION(1)  
TA  
PACKAGE(2)  
ORDERABLE PART NUMBER  
SN74LVC1G32IDCKREP  
SN74LVC1G32MDCKREP  
SN74LVC1G32MDBVREP  
TOP-SIDE MARKING(3)  
–40°C to 85°C  
SOT (SC-70) – DCK  
SOT (SC-70) – DCK  
Reel of 3000  
Reel of 3000  
CG0  
BYB  
–55°C to 125°C  
SOP (SOT-23) – DBV Reel of 3000  
SBGM  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(3) The actual top-side making has one additional character that designates the wafer fab/assembly site.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
A
H
X
L
B
X
H
L
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...15

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