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SN74LVC16244DGG

更新时间： 2024-11-20 13:13:51
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德州仪器 - TI 驱动器输出元件
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SN74LVC16244DGG 数据手册

 浏览型号SN74LVC16244DGG的Datasheet PDF文件第2页浏览型号SN74LVC16244DGG的Datasheet PDF文件第3页浏览型号SN74LVC16244DGG的Datasheet PDF文件第4页浏览型号SN74LVC16244DGG的Datasheet PDF文件第5页浏览型号SN74LVC16244DGG的Datasheet PDF文件第6页浏览型号SN74LVC16244DGG的Datasheet PDF文件第7页 
SN74LVC16244A  
16-BIT BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS699–AUGUST 2003–REVISED MARCH 2005  
FEATURES  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
•
Member of the Texas Instruments Widebus™  
Family  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OE  
1Y1  
1Y2  
GND  
1Y3  
1Y4  
2OE  
1A1  
1A2  
GND  
1A3  
1A4  
•
•
•
•
Operates From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.1 ns at 3.3 V  
2
3
4
Typical VOLP (Output Ground Bounce) < 0.8 V  
at VCC = 3.3 V, TA = 25°C  
5
6
•
•
•
Typical VOHV (Output VOH Undershoot) > 2 V  
at VCC = 3.3 V, TA = 25°C  
7
V
CC  
V
CC  
8
2Y1  
2Y2  
GND  
2Y3  
2Y4  
3Y1  
3Y2  
GND  
3Y3  
3Y4  
2A1  
2A2  
GND  
2A3  
2A4  
3A1  
3A2  
GND  
3A3  
3A4  
Ioff Supports Partial-Power-Down Mode  
Operation  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Supports Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With  
3.3-V VCC  
)
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 1000-V Charged-Device Model (C101)  
V
CC  
V
CC  
4Y1  
4Y2  
GND  
4Y3  
4Y4  
4OE  
4A1  
4A2  
GND  
4A3  
4A4  
3OE  
DESCRIPTION/ORDERING INFORMATION  
This 16-bit buffer/driver is designed for 1.65-V to  
3.6-V VCC operation.  
The SN74LVC16244A is designed specifically to  
improve the performance and density of 3-state  
memory address drivers, clock drivers, and  
bus-oriented receivers and transmitters.  
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and  
symmetrical active-low output-enable (OE) inputs.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in  
a mixed 3.3-V/5-V system environment.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74LVC16244AGRDR  
SN74LVC16244AZRDR  
SN74LVC16244ADL  
TOP-SIDE MARKING  
FBGA – GRD  
Tape and reel  
LD244A  
FBGA – ZRD (Pb-free)  
Tube  
SSOP – DL  
LVC16244A  
–40°C to 85°C  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
SN74LVC16244ADLR  
TSSOP – DGG  
TVSOP – DGV  
VFBGA – GQL  
SN74LVC16244ADGGR  
SN74LVC16244ADGVR  
SN74LVC16244AGQLR  
LVC16244A  
LD244A  
LD244A  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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