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SN74LV540APWLE PDF预览

SN74LV540APWLE

更新时间： 2024-11-06 19:48:03
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
7页 123K
描述
LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, PLASTIC, TSSOP-20

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SN74LV540APWLE 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP20,.25
针数：20Reach Compliance Code：not_compliant
风险等级：5.85其他特性：WITH DUAL OUTPUT ENABLE
控制类型：ENABLE LOW系列：LV/LV-A/LVX/H
JESD-30 代码：R-PDSO-G20长度：6.5 mm
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.008 A
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
Prop。Delay @ Nom-Sup：12 ns传播延迟（tpd）：18.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

SN74LV540APWLE 数据手册

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SN54LV540A, SN74LV540A  
OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCLS409C – APRIL 1998 – REVISED MAY 2000  
SN54LV540A . . . J OR W PACKAGE  
SN74LV540A . . . DB, DGV, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
OE1  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
CC  
OE2  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
Y1  
Y2  
Y3  
Y4  
A
2-V to 5.5-V V  
Operation  
CC  
Support Mixed-Mode Voltage Operation on  
All Ports  
Y5  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
13 Y6  
12 Y7  
ESD Protection Exceeds 2000 V Per  
11  
GND  
Y8  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
SN54LV540A . . . FK PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (DW, NS), Shrink  
Small-Outline (DB), Thin Very Small-Outline  
(DGV), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Flat (W) Packages, Chip  
Carriers (FK), and DIPs (J)  
3
2
1 20 19  
18  
Y1  
Y2  
Y3  
Y4  
Y5  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
17  
16  
15  
14  
description  
The ’LV540A devices are octal buffers/drivers  
designed for 2-V to 5.5-V V operation.  
9 10 11 12 13  
CC  
These devices are ideal for driving bus lines or  
buffer memory address registers. They feature  
inputs and outputs on opposite sides of the  
package to facilitate printed circuit board layout.  
The 3-state control gate is a two-input AND gate with active-low inputs so that if either output-enable (OE1 or  
OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide inverted data  
when they are not in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN54LV540A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74LV540A is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each buffer/driver)  
INPUTS  
OUTPUT  
Y
OE1  
L
OE2  
L
A
L
H
L
L
L
H
X
X
H
X
Z
Z
X
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments.  
Copyright 2000, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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