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SN74LS93N PDF预览

SN74LS93N

更新时间： 2024-02-05 12:31:25
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器
页数 文件大小 规格书
6页 113K
描述
DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER

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中文翻译

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SN74LS93N 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DFP, FL14,.3Reach Compliance Code：unknown
风险等级：5.56计数方向：UP
JESD-30 代码：R-XDFP-F14JESD-609代码：e0
负载/预设输入：NO逻辑集成电路类型：BINARY COUNTER
工作模式：ASYNCHRONOUS功能数量：1
端子数量：14最高工作温度：70 °C
最低工作温度：封装主体材料：CERAMIC
封装代码：DFP封装等效代码：FL14,.3
封装形状：RECTANGULAR封装形式：FLATPACK
电源：5 V认证状态：Not Qualified
子类别：Counters标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL

SN74LS93N 数据手册

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SN54/74LS90  
SN54/74LS92  
SN54/74LS93  
DECADE COUNTER;  
DIVIDE-BY-TWELVE COUNTER;  
4-BIT BINARY COUNTER  
DECADE COUNTER;  
DIVIDE-BY-TWELVE COUNTER;  
4-BIT BINARY COUNTER  
The SN54/74LS90, SN54/74LS92 and SN54/74LS93 are high-speed  
4-bit ripple type counters partitioned into two sections. Each counter has a di-  
vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or  
divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi-  
tion on the clock inputs. Each section can be used separately or tied together  
(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of  
the counters have a 2-input gated Master Reset (Clear), and the LS90 also  
has a 2-input gated Master Set (Preset 9).  
LOW POWER SCHOTTKY  
• Low Power Consumption . . . Typically 45 mW  
• High Count Rates . . . Typically 42 MHz  
• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,  
Binary  
J SUFFIX  
CERAMIC  
CASE 632-08  
14  
1
• Input Clamp Diodes Limit High Speed Termination Effects  
PIN NAMES  
LOADING (Note a)  
N SUFFIX  
HIGH  
LOW  
PLASTIC  
CASE 646-06  
CP  
CP  
CP  
Clock (Active LOW going edge) Input to  
÷2 Section  
0.5 U.L.  
1.5 U.L.  
0
1
1
14  
1
Clock (Active LOW going edge) Input to  
÷5 Section (LS90), ÷6 Section (LS92)  
0.5 U.L.  
0.5 U.L.  
2.0 U.L.  
1.0 U.L.  
Clock (Active LOW going edge) Input to  
÷8 Section (LS93)  
D SUFFIX  
SOIC  
CASE 751A-02  
MR , MR  
1
MS , MS  
Master Reset (Clear) Inputs  
0.5 U.L.  
0.5 U.L.  
10 U.L.  
10 U.L.  
0.25 U.L.  
0.25 U.L.  
5 (2.5) U.L.  
5 (2.5) U.L.  
2
2
14  
Master Set (Preset-9, LS90) Inputs  
Output from ÷2 Section (Notes b & c)  
Outputs from ÷5 (LS90), ÷6 (LS92),  
÷ 8 (LS93) Sections (Note b)  
1
1
Q
0
Q , Q , Q  
1 3  
2
ORDERING INFORMATION  
NOTES:  
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)  
b. Temperature Ranges.  
SN54LSXXJ  
SN74LSXXN  
SN74LSXXD  
Ceramic  
Plastic  
SOIC  
c. The Q Outputs are guaranteed to drive the full fan-out plus the CP input of the device.  
0
1
d. To insure proper operation the rise (t ) and fall time (t ) of the clock must be less than 100 ns.  
r
f
LOGIC SYMBOL  
LS92  
LS90  
LS93  
6
1
7
2
MS  
14  
1
CP  
CP  
14  
1
CP  
0
14  
1
CP  
CP  
0
0
CP  
1
1
1
MR  
Q Q Q Q  
0 1 2 3  
MR  
Q Q Q Q  
0 1 2 3  
MR  
Q Q Q Q  
0 1 2 3  
1 2  
1
2
7
1
2
2
3
12  
9
8 11  
2
3
12  
9
8
11  
6
12 11  
= PIN 5  
9
8
V
= PIN 5  
V
V
= PIN 5  
CC  
CC  
GND = PIN 10  
NC = PINS 2, 3, 4, 13  
CC  
GND = PIN 10  
NC = PIN 4, 6, 7, 13  
GND = PIN 10  
NC = PINS 4, 13  
FAST AND LS TTL DATA  
5-90  
123456

中文翻译

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