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SN74LS92DR2 PDF预览

SN74LS92DR2

更新时间： 2024-11-26 15:52:19
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
7页 166K
描述
LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DIVIDE BY 12 COUNTER, PDSO14, SOIC-14

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SN74LS92DR2 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.15Is Samacsys：N
其他特性：ONE FUNCTION HAS 1 BIT计数方向：UP
系列：LSJESD-30 代码：R-PDSO-G14
长度：8.65 mm负载/预设输入：YES
逻辑集成电路类型：DIVIDE BY 12 COUNTER工作模式：ASYNCHRONOUS
位数：3功能数量：2
端子数量：14最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE传播延迟（tpd）：50 ns
认证状态：Not Qualified座面最大高度：1.75 mm
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL触发器类型：NEGATIVE EDGE
宽度：3.9 mm最小 fmax：32 MHz
Base Number Matches：1

SN74LS92DR2 数据手册

 浏览型号SN74LS92DR2的Datasheet PDF文件第2页浏览型号SN74LS92DR2的Datasheet PDF文件第3页浏览型号SN74LS92DR2的Datasheet PDF文件第4页浏览型号SN74LS92DR2的Datasheet PDF文件第5页浏览型号SN74LS92DR2的Datasheet PDF文件第6页浏览型号SN74LS92DR2的Datasheet PDF文件第7页 
SN74LS90  
DECADE COUNTER;  
DIVIDE-BY-TWELVE  
COUNTER;  
4-BIT BINARY COUNTER  
http://onsemi.com  
The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are  
high-speed 4-bit ripple type counters partitioned into two sections.  
Each counter has a divide-by-two section and either a divide-by-five  
(LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which  
are triggered by a HIGH-to-LOW transition on the clock inputs. Each  
section can be used separately or tied together (Q to CP) to form BCD,  
bi-quinary, modulo-12, or modulo-16 counters. All of the counters  
have a 2-input gated Master Reset (Clear), and the LS90 also has a  
2-input gated Master Set (Preset 9).  
DECADE COUNTER;  
DIVIDE-BY-TWELVE COUNTER;  
4-BIT BINARY COUNTER  
LOW POWER SCHOTTKY  
• Low Power Consumption . . . Typically 45 mW  
• High Count Rates . . . Typically 42 MHz  
J SUFFIX  
CERAMIC  
CASE 632-08  
• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,  
Binary  
• Input Clamp Diodes Limit High Speed Termination Effects  
14  
1
PIN NAMES  
LOADING (Note a)  
HIGH  
LOW  
N SUFFIX  
PLASTIC  
CASE 646-06  
CP  
CP  
CP  
Clock (Active LOW going edge) Input to  
÷2 Section  
Clock (Active LOW going edge) Input to  
÷5 Section (LS90), ÷6 Section (LS92)  
0.5 U.L.  
1.5 U.L.  
0
1
1
0.5 U.L.  
0.5 U.L.  
2.0 U.L.  
1.0 U.L.  
14  
1
Clock (Active LOW going edge) Input to  
÷8 Section (LS93)  
MR , MR  
Master Reset (Clear) Inputs  
0.5 U.L.  
0.5 U.L.  
10 U.L.  
10 U.L.  
0.25 U.L.  
0.25 U.L.  
5 (2.5) U.L.  
5 (2.5) U.L.  
1
2
2
D SUFFIX  
SOIC  
CASE 751A-02  
MS , MS  
Master Set (Preset-9, LS90) Inputs  
Output from ÷2 Section (Notes b & c)  
Outputs from ÷5 (LS90), ÷6 (LS92),  
÷8 (LS93) Sections (Note b)  
1
Q
14  
0
1
Q , Q , Q  
3
1
2
NOTES:  
a. 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.  
ORDERING INFORMATION  
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)  
b. Temperature Ranges.  
SN54LSXXJ  
SN74LSXXN  
SN74LSXXD  
Ceramic  
Plastic  
SOIC  
c. The Q Outputs are guaranteed to drive the full fan-out plus the CP input of the device.  
0
1
d. To insure proper operation the rise (t ) and fall time (t ) of the clock must be less than 100 ns.  
r
f
LOGIC SYMBOL  
LS92  
6
7
1 2  
LS90  
LS93  
MS  
14  
CP  
CP  
14  
1
CP  
14  
1
CP  
CP  
0
1
0
0
CP  
1
1
1
MR  
Q Q Q Q  
0 1 2 3  
MR  
Q
Q
Q
9
Q
8
MR  
Q
Q Q Q  
0 1 2 3  
0
1
2
3
1 2  
1 2  
1
2
2 3 12 9  
V = PIN 5  
CC  
8 11  
2 3 12  
9
8 11  
6 7 12 11  
= PIN 5  
V
= PIN 5  
V
CC  
CC  
GND = PIN 10  
GND = PIN 10  
GND = PIN 10  
NC = PIN 4, 6, 7, 13  
NC = PINS 4, 13  
NC = PINS 2, 3, 4, 13  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
SN74LS90/D  
July, 2006 − Rev. 6  
1234567

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SN74LS92DR2 替代型号

型号 品牌 替代类型 描述 数据表
SN74LS92D ONSEMI

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 DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER

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