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SN74LS379NS PDF预览

SN74LS379NS

更新时间: 2024-11-02 13:13:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器
页数 文件大小 规格书
7页 253K
描述
LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16, PLASTIC, DIP-16

SN74LS379NS 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.68
其他特性:WITH HOLD MODE系列:LS
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
长度:20.07 mm逻辑集成电路类型:D FLIP-FLOP
位数:4功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):27 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:FF/Latches最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:40 MHzBase Number Matches:1

SN74LS379NS 数据手册

 浏览型号SN74LS379NS的Datasheet PDF文件第2页浏览型号SN74LS379NS的Datasheet PDF文件第3页浏览型号SN74LS379NS的Datasheet PDF文件第4页浏览型号SN74LS379NS的Datasheet PDF文件第5页浏览型号SN74LS379NS的Datasheet PDF文件第6页浏览型号SN74LS379NS的Datasheet PDF文件第7页 
SN54/74LS377  
SN54/74LS378  
SN54/74LS379  
OCTAL D FLIP-FLOP WITH ENABLE;  
HEX D FLIP-FLOP WITH ENABLE;  
4-BIT D FLIP-FLOP WITH ENABLE  
OCTAL D FLIP-FLOP WITH  
ENABLE; HEX D FLIP-FLOP  
WITH ENABLE; 4-BIT D FLIP-FLOP  
WITH ENABLE  
The SN54/74LS377 is an 8-bit register built using advanced Low Power  
Schottky technology. This register consists of eight D-type flip-flops with a  
buffered common clock and a buffered common clock enable.  
The SN54/74LS378 is a 6-Bit Register with a buffered common enable.  
This device is similar to the SN54/74LS174, but with common Enable rather  
than common Master Reset.  
LOW POWER SCHOTTKY  
The SN54/74LS379 is a 4-Bit Register with buffered common Enable. This  
device is similar to the SN54/74LS175 but features the common Enable  
rather then common Master Reset.  
J SUFFIX  
CERAMIC  
8-Bit High Speed Parallel Registers  
CASE 732-03  
Positive Edge-Triggered D-Type Flip Flops  
Fully Buffered Common Clock and Enable Inputs  
True and Complement Outputs  
20  
1
Input Clamp Diodes Limit High Speed Termination Effects  
N SUFFIX  
PLASTIC  
CASE 738-03  
PIN NAMES  
LOADING (Note a)  
20  
1
HIGH  
LOW  
E
Enable (Active LOW) Input  
Data Inputs  
Clock (Active HIGH Going Edge) Input  
True Outputs (Note b)  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
10 U.L.  
10 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
5 (2.5) U.L.  
5 (2.5) U.L.  
D D  
CP  
Q Q  
Q Q  
0
3
DW SUFFIX  
SOIC  
CASE 751D-03  
20  
0
0
3
3
1
Complemented Outputs (Note b)  
NOTES:  
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial  
(74) Temperature Ranges.  
J SUFFIX  
CERAMIC  
CASE 620-09  
16  
1
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
1
D SUFFIX  
SOIC  
CASE 751B-03  
16  
1
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXDW SOIC  
SN74LSXXXD SOIC  
FAST AND LS TTL DATA  
5-533  

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