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SN74LS348JDS PDF预览

SN74LS348JDS

更新时间: 2024-12-01 13:13:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 输出元件输入元件编码器
页数 文件大小 规格书
6页 219K
描述
LS SERIES, 8-BIT ENCODER, CDIP16, CERAMIC, DIP-16

SN74LS348JDS 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.24Is Samacsys:N
其他特性:8 TO 3 LINE PRIORITY ENCODER; CASCADABLE; WITH GROUP SELECT OUTPUT系列:LS
JESD-30 代码:R-GDIP-T16JESD-609代码:e0
长度:19.495 mm逻辑集成电路类型:ENCODER
位数:8功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):35 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Arithmetic Circuits最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

SN74LS348JDS 数据手册

 浏览型号SN74LS348JDS的Datasheet PDF文件第2页浏览型号SN74LS348JDS的Datasheet PDF文件第3页浏览型号SN74LS348JDS的Datasheet PDF文件第4页浏览型号SN74LS348JDS的Datasheet PDF文件第5页浏览型号SN74LS348JDS的Datasheet PDF文件第6页 
SN54/74LS348  
SN54/74LS848  
8-INPUT PRIORITY ENCODERS  
WITH 3-STATE OUTPUTS  
The SN54/74LS348 and the SN54/74LS848 are eight input priority encod-  
ers which provide the 8-line to 3-line function.  
The outputs (A0A2) and inputs (07) are active low. The active low input  
which has the highest priority (input 7 has the highest) is represented on the  
outputs (output A0 is the lowest bit). An example would be if inputs 1, 2 and 4  
were low, then a binary 4 would be represented on the outputs.  
The GS (Group Signal) output is active low when any of the inputs are low. It  
serves to indicate when any of the inputs are active.  
8-INPUT PRIORITY ENCODERS  
WITH 3-STATE OUTPUTS  
LOW POWER SCHOTTKY  
A0, A1 and A2 are three-state outputs. This allows for up to 64 line expan-  
sion without the need for special external circuitry.  
A logical one on the Enable Input (EI) forces A0, A1 ared A2 to the disabled  
state and outputs GS and EO to the high state. A high on all data inputs (07)  
together with a low on the EI input disables outputs A0, A1, and A2 and forces  
output GS to the high state and output EO to the low state.  
Use of the EI input in conjunction with the EO output provides for the capa-  
bility of having priority encoding of n input signals.  
J SUFFIX  
CERAMIC  
CASE 620-09  
16  
1
TheLS848hasspecialinternalcircuitryprovidingforagreatlyreducedneg-  
ative going glitch on the GS (Group Signal) output and on a reduced tendency  
for the A0, A1 and A2 outputs to become momentarily enabled. Both of these  
occurrenceshappenwhentheEIinputgoesfromalogicalonetoalogicalzero  
and all data inputs (07) are held at logical ones. The internal glitch reduction  
circuitry does add an additional fan-in of one on all data inputs (compared to  
that of the LS348).  
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
1
D SUFFIX  
SOIC  
CASE 751B-03  
16  
1
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
EI  
0
1
2
3
4
5
6
7
A2 A1 A0 GS EO  
H
L
L
L
L
L
L
L
L
L
X
H
X
X
X
X
X
X
X
L
X
H
X
X
X
X
X
X
L
X
H
X
X
X
X
X
L
X
H
X
X
X
X
L
H
H
H
X
H
X
X
X
L
H
H
H
H
X
H
X
X
L
H
H
H
H
H
X
H
X
L
H
H
H
H
H
H
X
H
L
H
H
H
H
H
H
H
Z
Z
L
L
L
Z
Z
L
Z
Z
L
H
L
H
L
H
L
H
H
L
L
L
L
L
L
L
L
H
L
H = HIGH Logic Level  
L = LOW Logic Level  
X = Irrelevant  
H
H
H
H
H
H
H
H
L
Z = High Impedance State  
H
H
L
L
H
H
L
H
H
H
H
H
H
H
H
FAST AND LS TTL DATA  
5-499  

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