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SN74LS348ND

更新时间: 2024-01-30 00:48:30
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摩托罗拉 - MOTOROLA 输出元件输入元件编码器
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SN74LS348ND 数据手册

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SN54/74LS348  
SN54/74LS848  
8-INPUT PRIORITY ENCODERS  
WITH 3-STATE OUTPUTS  
The SN54/74LS348 and the SN54/74LS848 are eight input priority encod-  
ers which provide the 8-line to 3-line function.  
The outputs (A0A2) and inputs (07) are active low. The active low input  
which has the highest priority (input 7 has the highest) is represented on the  
outputs (output A0 is the lowest bit). An example would be if inputs 1, 2 and 4  
were low, then a binary 4 would be represented on the outputs.  
The GS (Group Signal) output is active low when any of the inputs are low. It  
serves to indicate when any of the inputs are active.  
8-INPUT PRIORITY ENCODERS  
WITH 3-STATE OUTPUTS  
LOW POWER SCHOTTKY  
A0, A1 and A2 are three-state outputs. This allows for up to 64 line expan-  
sion without the need for special external circuitry.  
A logical one on the Enable Input (EI) forces A0, A1 ared A2 to the disabled  
state and outputs GS and EO to the high state. A high on all data inputs (07)  
together with a low on the EI input disables outputs A0, A1, and A2 and forces  
output GS to the high state and output EO to the low state.  
Use of the EI input in conjunction with the EO output provides for the capa-  
bility of having priority encoding of n input signals.  
J SUFFIX  
CERAMIC  
CASE 620-09  
16  
1
TheLS848hasspecialinternalcircuitryprovidingforagreatlyreducedneg-  
ative going glitch on the GS (Group Signal) output and on a reduced tendency  
for the A0, A1 and A2 outputs to become momentarily enabled. Both of these  
occurrenceshappenwhentheEIinputgoesfromalogicalonetoalogicalzero  
and all data inputs (07) are held at logical ones. The internal glitch reduction  
circuitry does add an additional fan-in of one on all data inputs (compared to  
that of the LS348).  
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
1
D SUFFIX  
SOIC  
CASE 751B-03  
16  
1
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
EI  
0
1
2
3
4
5
6
7
A2 A1 A0 GS EO  
H
L
L
L
L
L
L
L
L
L
X
H
X
X
X
X
X
X
X
L
X
H
X
X
X
X
X
X
L
X
H
X
X
X
X
X
L
X
H
X
X
X
X
L
H
H
H
X
H
X
X
X
L
H
H
H
H
X
H
X
X
L
H
H
H
H
H
X
H
X
L
H
H
H
H
H
H
X
H
L
H
H
H
H
H
H
H
Z
Z
L
L
L
Z
Z
L
Z
Z
L
H
L
H
L
H
L
H
H
L
L
L
L
L
L
L
L
H
L
H = HIGH Logic Level  
L = LOW Logic Level  
X = Irrelevant  
H
H
H
H
H
H
H
H
L
Z = High Impedance State  
H
H
L
L
H
H
L
H
H
H
H
H
H
H
H
FAST AND LS TTL DATA  
5-499  

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