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SN74LS299NDS PDF预览

SN74LS299NDS

更新时间: 2024-11-29 13:13:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器存储触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
7页 258K
描述
LS SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP20, 738-01

SN74LS299NDS 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP20,.3
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.22
其他特性:HOLD MODE; COMMON I/O PINS; TOTEMPOLE SERIAL SHIFT RIGHT & SHIFT LEFT OUTPUTS; GATED OUTPUT CONTROL计数方向:BIDIRECTIONAL
系列:LSJESD-30 代码:R-PDIP-T20
JESD-609代码:e0长度:26.415 mm
逻辑集成电路类型:PARALLEL IN PARALLEL OUT位数:8
功能数量:1端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):39 ns
认证状态:Not Qualified座面最大高度:4.19 mm
子类别:Shift Registers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:35 MHzBase Number Matches:1

SN74LS299NDS 数据手册

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SN54/74LS299  
8-BIT SHIFT/STORAGE REGISTER  
WITH 3-STATE OUTPUTS  
The SN54/74LS299 is an 8-Bit Universal Shift/Storage Register with  
3-state outputs. Four modes of operation are possible: hold (store), shift left,  
shift right and load data.  
8-BIT SHIFT/STORAGE REGISTER  
WITH 3-STATE OUTPUTS  
The parallel load inputs and flip-flop outputs are multiplexed to reduce the  
LOW POWER SCHOTTKY  
total number of package pins. Separate outputs are provided for flip-flops Q  
0
and Q to allow easy cascading. A separate active LOW Master Reset is used  
7
to reset the register.  
Common I/O for Reduced Pin Count  
Four Operation Modes: Shift Left, Shift Right, Load and Store  
Separate Shift Right Serial Input and Shift Left Serial Input for Easy  
Cascading  
3-State Outputs for Bus Oriented Applications  
Input Clamp Diodes Limit High-Speed Termination Effects  
ESD > 3500 Volts  
J SUFFIX  
CERAMIC  
CASE 732-03  
20  
1
N SUFFIX  
PLASTIC  
CASE 738-03  
20  
CONNECTION DIAGRAM DIP (TOP VIEW)  
1
DW SUFFIX  
SOIC  
CASE 751D-03  
20  
NOTE:  
1
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXDW SOIC  
PIN NAMES  
LOADING (Note a)  
HIGH  
LOW  
CP  
DS0  
DS7  
Clock Pulse (active positive-going edge) Input  
Serial Data Input for Right Shift  
Serial Data Input for Left Shift  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
I/O  
Parallel Data Input or  
n
65 (25) U.L.  
0.5 U.L.  
10 U.L.  
15 (7.5) U.L.  
0.25 U.L.  
5 (2.5) U.L.  
0.25 U.L.  
0.5 U.L.  
Parallel Output (3-State) (Note c)  
3-State Output Enable (active LOW) Inputs  
Serial Outputs (Note b)  
Asynchronous Master Reset (active LOW) Input  
Mode Select Inputs  
OE , OE  
1
2
Q , Q  
0
7
MR  
0.5 U.L.  
1 U.L.  
S , S  
0
1
NOTES:  
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b) The Output LOW drive factor is 2.5 U.L for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.  
c) The Output LOW drive factor is 7.5 U.L for Military (54) and 15 U.L. for Commercial (74). The Output HIGH drive factor is 25 U.L. for Military (54) and 65 U.L. for  
Commercial (74) Temperature Ranges.  
FAST AND LS TTL DATA  
5-479  

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